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authorKevin Lim <ktlim@umich.edu>2006-07-12 17:16:00 -0400
committerKevin Lim <ktlim@umich.edu>2006-07-12 17:16:00 -0400
commit35ab2296d3eec6da29ba30a6230f67433f261eb3 (patch)
tree2743550ebc4697210037df00d9aef641e9e9b6f2 /src/python/m5/objects/Ethernet.py
parent807afe829261f28d9cdbddc81e6e2b4b58c74f2f (diff)
downloadgem5-35ab2296d3eec6da29ba30a6230f67433f261eb3.tar.xz
Push more default options to the Python object level as they are rarely changed. These are the changes that Steve was working on.
src/python/m5/objects/DiskImage.py: src/python/m5/objects/Ethernet.py: src/python/m5/objects/Ide.py: src/python/m5/objects/Tsunami.py: Push more default options to the Python object level as they are rarely changed. --HG-- extra : convert_revision : 963eb7a34cd04529b3c5f24b92904ab725c93efb
Diffstat (limited to 'src/python/m5/objects/Ethernet.py')
-rw-r--r--src/python/m5/objects/Ethernet.py45
1 files changed, 44 insertions, 1 deletions
diff --git a/src/python/m5/objects/Ethernet.py b/src/python/m5/objects/Ethernet.py
index 418670592..db7efe004 100644
--- a/src/python/m5/objects/Ethernet.py
+++ b/src/python/m5/objects/Ethernet.py
@@ -1,7 +1,7 @@
from m5 import build_env
from m5.config import *
from Device import DmaDevice
-from Pci import PciDevice
+from Pci import PciDevice, PciConfigData
class EtherInt(SimObject):
type = 'EtherInt'
@@ -84,6 +84,26 @@ class EtherDevBase(PciDevice):
tx_thread = Param.Bool(False, "dedicated kernel threads for receive")
rss = Param.Bool(False, "Receive Side Scaling")
+class NSGigEPciData(PciConfigData):
+ VendorID = 0x100B
+ DeviceID = 0x0022
+ Status = 0x0290
+ SubClassCode = 0x00
+ ClassCode = 0x02
+ ProgIF = 0x00
+ BAR0 = 0x00000001
+ BAR1 = 0x00000000
+ BAR2 = 0x00000000
+ BAR3 = 0x00000000
+ BAR4 = 0x00000000
+ BAR5 = 0x00000000
+ MaximumLatency = 0x34
+ MinimumGrant = 0xb0
+ InterruptLine = 0x1e
+ InterruptPin = 0x01
+ BAR0Size = '256B'
+ BAR1Size = '4kB'
+
class NSGigE(EtherDevBase):
type = 'NSGigE'
@@ -91,11 +111,32 @@ class NSGigE(EtherDevBase):
dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
dma_no_allocate = Param.Bool(True, "Should we allocate cache on read")
+ configdata = NSGigEPciData()
+
class NSGigEInt(EtherInt):
type = 'NSGigEInt'
device = Param.NSGigE("Ethernet device of this interface")
+class SinicPciData(PciConfigData):
+ VendorID = 0x1291
+ DeviceID = 0x1293
+ Status = 0x0290
+ SubClassCode = 0x00
+ ClassCode = 0x02
+ ProgIF = 0x00
+ BAR0 = 0x00000000
+ BAR1 = 0x00000000
+ BAR2 = 0x00000000
+ BAR3 = 0x00000000
+ BAR4 = 0x00000000
+ BAR5 = 0x00000000
+ MaximumLatency = 0x34
+ MinimumGrant = 0xb0
+ InterruptLine = 0x1e
+ InterruptPin = 0x01
+ BAR0Size = '64kB'
+
class Sinic(EtherDevBase):
type = 'Sinic'
@@ -111,6 +152,8 @@ class Sinic(EtherDevBase):
delay_copy = Param.Bool(False, "Delayed copy transmit")
virtual_addr = Param.Bool(False, "Virtual addressing")
+ configdata = SinicPciData()
+
class SinicInt(EtherInt):
type = 'SinicInt'
device = Param.Sinic("Ethernet device of this interface")