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authorKevin Lim <ktlim@umich.edu>2006-10-08 01:12:42 -0400
committerKevin Lim <ktlim@umich.edu>2006-10-08 01:12:42 -0400
commit8949d813ff6f9941faf1b173d408e13b0a2440a7 (patch)
treef6be6522df707fc907710a9b234a93fdbe8ca13e /src/python/m5/objects/FuncUnitConfig.py
parentb17421da2059935f7951f3ac963eae7ff6db4a3c (diff)
downloadgem5-8949d813ff6f9941faf1b173d408e13b0a2440a7.tar.xz
Clean up configs.
configs/common/FSConfig.py: configs/common/SysPaths.py: configs/example/fs.py: configs/example/se.py: tests/configs/o3-timing-mp.py: tests/configs/o3-timing.py: Clean up configs by removing FullO3Config and instead using default values. src/python/m5/objects/FUPool.py: Add in default FUPool. src/python/m5/objects/O3CPU.py: Use defaults better. Also set checker parameters, and fix up a config bug. --HG-- extra : convert_revision : 5fd0c000143f4881f10a9a575c3810dc97cb290b
Diffstat (limited to 'src/python/m5/objects/FuncUnitConfig.py')
-rw-r--r--src/python/m5/objects/FuncUnitConfig.py41
1 files changed, 41 insertions, 0 deletions
diff --git a/src/python/m5/objects/FuncUnitConfig.py b/src/python/m5/objects/FuncUnitConfig.py
new file mode 100644
index 000000000..43d7a4bb7
--- /dev/null
+++ b/src/python/m5/objects/FuncUnitConfig.py
@@ -0,0 +1,41 @@
+from m5.SimObject import SimObject
+from m5.params import *
+from FuncUnit import *
+
+class IntALU(FUDesc):
+ opList = [ OpDesc(opClass='IntAlu') ]
+ count = 6
+
+class IntMultDiv(FUDesc):
+ opList = [ OpDesc(opClass='IntMult', opLat=3),
+ OpDesc(opClass='IntDiv', opLat=20, issueLat=19) ]
+ count=2
+
+class FP_ALU(FUDesc):
+ opList = [ OpDesc(opClass='FloatAdd', opLat=2),
+ OpDesc(opClass='FloatCmp', opLat=2),
+ OpDesc(opClass='FloatCvt', opLat=2) ]
+ count = 4
+
+class FP_MultDiv(FUDesc):
+ opList = [ OpDesc(opClass='FloatMult', opLat=4),
+ OpDesc(opClass='FloatDiv', opLat=12, issueLat=12),
+ OpDesc(opClass='FloatSqrt', opLat=24, issueLat=24) ]
+ count = 2
+
+class ReadPort(FUDesc):
+ opList = [ OpDesc(opClass='MemRead') ]
+ count = 0
+
+class WritePort(FUDesc):
+ opList = [ OpDesc(opClass='MemWrite') ]
+ count = 0
+
+class RdWrPort(FUDesc):
+ opList = [ OpDesc(opClass='MemRead'), OpDesc(opClass='MemWrite') ]
+ count = 4
+
+class IprPort(FUDesc):
+ opList = [ OpDesc(opClass='IprAccess', opLat = 3, issueLat = 3) ]
+ count = 1
+