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authorKevin Lim <ktlim@umich.edu>2006-07-11 13:43:30 -0400
committerKevin Lim <ktlim@umich.edu>2006-07-11 13:43:30 -0400
commit0b0cb2bca71acdab4a30acc639509030631f9dfd (patch)
treefee4bbd0c1bfb45b7abec14e944400852f90b468 /src/python/m5/objects/OzoneCPU.py
parentb55cda163ed1a29ee5e08cde36743047923ab475 (diff)
parent7078d8d1b42c1a158c854b3e07800f20aa695bfb (diff)
downloadgem5-0b0cb2bca71acdab4a30acc639509030631f9dfd.tar.xz
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem --HG-- extra : convert_revision : c565fd7cebaa4058ba510b3db50a9c76bf301228
Diffstat (limited to 'src/python/m5/objects/OzoneCPU.py')
-rw-r--r--src/python/m5/objects/OzoneCPU.py3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/python/m5/objects/OzoneCPU.py b/src/python/m5/objects/OzoneCPU.py
index 8aff89203..88fb63c74 100644
--- a/src/python/m5/objects/OzoneCPU.py
+++ b/src/python/m5/objects/OzoneCPU.py
@@ -9,6 +9,9 @@ class DerivOzoneCPU(BaseCPU):
checker = Param.BaseCPU("Checker CPU")
+ icache_port = Port("Instruction Port")
+ dcache_port = Port("Data Port")
+
width = Param.Unsigned("Width")
frontEndWidth = Param.Unsigned("Front end width")
backEndWidth = Param.Unsigned("Back end width")