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authorKevin Lim <ktlim@umich.edu>2006-07-07 18:24:13 -0400
committerKevin Lim <ktlim@umich.edu>2006-07-07 18:24:13 -0400
commit43245d9c2f3986430c1fbc4a09ee90096f6d3f30 (patch)
treeae63a7cbf3c5a4a89225ce3d1da2514d3da9c2e2 /src/python/m5/objects/OzoneCPU.py
parent8ade33d324218737c815935120307153975eeadc (diff)
downloadgem5-43245d9c2f3986430c1fbc4a09ee90096f6d3f30.tar.xz
Support for recent port changes.
src/cpu/ozone/cpu.hh: src/cpu/ozone/cpu_impl.hh: src/cpu/ozone/front_end.hh: src/cpu/ozone/front_end_impl.hh: src/cpu/ozone/lw_back_end.hh: src/cpu/ozone/lw_lsq.hh: src/cpu/ozone/lw_lsq_impl.hh: src/python/m5/objects/OzoneCPU.py: Support Ron's recent port changes. src/cpu/ozone/lw_back_end_impl.hh: Support Ron's recent port changes. Also support handling faults in SE. --HG-- extra : convert_revision : aa1ba5111b70199c052da3e13bae605525a69891
Diffstat (limited to 'src/python/m5/objects/OzoneCPU.py')
-rw-r--r--src/python/m5/objects/OzoneCPU.py3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/python/m5/objects/OzoneCPU.py b/src/python/m5/objects/OzoneCPU.py
index 8aff89203..88fb63c74 100644
--- a/src/python/m5/objects/OzoneCPU.py
+++ b/src/python/m5/objects/OzoneCPU.py
@@ -9,6 +9,9 @@ class DerivOzoneCPU(BaseCPU):
checker = Param.BaseCPU("Checker CPU")
+ icache_port = Port("Instruction Port")
+ dcache_port = Port("Data Port")
+
width = Param.Unsigned("Width")
frontEndWidth = Param.Unsigned("Front end width")
backEndWidth = Param.Unsigned("Back end width")