Move SimObject python files alongside the C++ and fix

the SConscript files so that only the objects that are
actually available in a given build are compiled in.
Remove a bunch of files that aren't used anymore.

--HG--
rename : src/python/m5/objects/AlphaTLB.py => src/arch/alpha/AlphaTLB.py
rename : src/python/m5/objects/SparcTLB.py => src/arch/sparc/SparcTLB.py
rename : src/python/m5/objects/BaseCPU.py => src/cpu/BaseCPU.py
rename : src/python/m5/objects/FuncUnit.py => src/cpu/FuncUnit.py
rename : src/python/m5/objects/IntrControl.py => src/cpu/IntrControl.py
rename : src/python/m5/objects/MemTest.py => src/cpu/memtest/MemTest.py
rename : src/python/m5/objects/FUPool.py => src/cpu/o3/FUPool.py
rename : src/python/m5/objects/FuncUnitConfig.py => src/cpu/o3/FuncUnitConfig.py
rename : src/python/m5/objects/O3CPU.py => src/cpu/o3/O3CPU.py
rename : src/python/m5/objects/OzoneCPU.py => src/cpu/ozone/OzoneCPU.py
rename : src/python/m5/objects/SimpleOzoneCPU.py => src/cpu/ozone/SimpleOzoneCPU.py
rename : src/python/m5/objects/BadDevice.py => src/dev/BadDevice.py
rename : src/python/m5/objects/Device.py => src/dev/Device.py
rename : src/python/m5/objects/DiskImage.py => src/dev/DiskImage.py
rename : src/python/m5/objects/Ethernet.py => src/dev/Ethernet.py
rename : src/python/m5/objects/Ide.py => src/dev/Ide.py
rename : src/python/m5/objects/Pci.py => src/dev/Pci.py
rename : src/python/m5/objects/Platform.py => src/dev/Platform.py
rename : src/python/m5/objects/SimConsole.py => src/dev/SimConsole.py
rename : src/python/m5/objects/SimpleDisk.py => src/dev/SimpleDisk.py
rename : src/python/m5/objects/Uart.py => src/dev/Uart.py
rename : src/python/m5/objects/AlphaConsole.py => src/dev/alpha/AlphaConsole.py
rename : src/python/m5/objects/Tsunami.py => src/dev/alpha/Tsunami.py
rename : src/python/m5/objects/T1000.py => src/dev/sparc/T1000.py
rename : src/python/m5/objects/Bridge.py => src/mem/Bridge.py
rename : src/python/m5/objects/Bus.py => src/mem/Bus.py
rename : src/python/m5/objects/MemObject.py => src/mem/MemObject.py
rename : src/python/m5/objects/PhysicalMemory.py => src/mem/PhysicalMemory.py
rename : src/python/m5/objects/BaseCache.py => src/mem/cache/BaseCache.py
rename : src/python/m5/objects/CoherenceProtocol.py => src/mem/cache/coherence/CoherenceProtocol.py
rename : src/python/m5/objects/Repl.py => src/mem/cache/tags/Repl.py
rename : src/python/m5/objects/Process.py => src/sim/Process.py
rename : src/python/m5/objects/Root.py => src/sim/Root.py
rename : src/python/m5/objects/System.py => src/sim/System.py
extra : convert_revision : 173f8764bafa8ef899198438fa5573874e407321

1 files changed, 0 insertions, 29 deletions

diff --git a/src/python/m5/objects/PhysicalMemory.py b/src/python/m5/objects/PhysicalMemory.py
deleted file mode 100644
index 83dbc7710..000000000
--- a/src/python/m5/objects/PhysicalMemory.py
+++ /dev/null
@@ -1,29 +0,0 @@
-from m5.params import *
-from m5.proxy import *
-from MemObject import *
-
-class PhysicalMemory(MemObject):
-    type = 'PhysicalMemory'
-    port = VectorPort("the access port")
-    range = Param.AddrRange(AddrRange('128MB'), "Device Address")
-    file = Param.String('', "memory mapped file")
-    latency = Param.Latency('1t', "latency of an access")
-    zero = Param.Bool(False, "zero initialize memory")
-
-class DRAMMemory(PhysicalMemory):
-    type = 'DRAMMemory'
-    # Many of these should be observed from the configuration
-    cpu_ratio = Param.Int(5,"ratio between CPU speed and memory bus speed")
-    mem_type = Param.String("SDRAM", "Type of DRAM (DRDRAM, SDRAM)")
-    mem_actpolicy = Param.String("open", "Open/Close policy")
-    memctrladdr_type = Param.String("interleaved", "Mapping interleaved or direct")
-    bus_width = Param.Int(16, "")
-    act_lat = Param.Int(2, "RAS to CAS delay")
-    cas_lat = Param.Int(1, "CAS delay")
-    war_lat = Param.Int(2, "write after read delay")
-    pre_lat = Param.Int(2, "precharge delay")
-    dpl_lat = Param.Int(2, "data in to precharge delay")
-    trc_lat = Param.Int(6, "row cycle delay")
-    num_banks = Param.Int(4, "Number of Banks")
-    num_cpus = Param.Int(4, "Number of CPUs connected to DRAM")
-