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authorGabe Black <gblack@eecs.umich.edu>2007-02-23 12:54:07 +0000
committerGabe Black <gblack@eecs.umich.edu>2007-02-23 12:54:07 +0000
commitc0c3a3f491aa02d237cb0d918c962572b547634a (patch)
treee7a40ef9dab946f8d9bf5287b04d796c4330e05f /src/python/m5/objects/T1000.py
parentf8ffc84d0b4fc908487a0af200abcc3cfce56633 (diff)
parenta5b73a6e332c3f27ce29346229e1f91c04f53cf9 (diff)
downloadgem5-c0c3a3f491aa02d237cb0d918c962572b547634a.tar.xz
Merge zizzer.eecs.umich.edu:/bk/newmem
into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem --HG-- extra : convert_revision : e0eb0240848698496bd55093a313eb2e0f512ebc
Diffstat (limited to 'src/python/m5/objects/T1000.py')
-rw-r--r--src/python/m5/objects/T1000.py6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/python/m5/objects/T1000.py b/src/python/m5/objects/T1000.py
index 3ab6d4283..aeca491c4 100644
--- a/src/python/m5/objects/T1000.py
+++ b/src/python/m5/objects/T1000.py
@@ -3,7 +3,7 @@ from m5.proxy import *
from Device import BasicPioDevice, IsaFake, BadAddr
from Uart import Uart8250
from Platform import Platform
-from SimConsole import SimConsole, ConsoleListener
+from SimConsole import SimConsole
class MmDisk(BasicPioDevice):
@@ -69,11 +69,11 @@ class T1000(Platform):
fake_ssi = IsaFake(pio_addr=0xff00000000, pio_size=0x10000000)
#warn_access="Accessing SSI -- Unimplemented!")
- hconsole = SimConsole(listener = ConsoleListener())
+ hconsole = SimConsole()
hvuart = Uart8250(pio_addr=0xfff0c2c000)
htod = DumbTOD()
- pconsole = SimConsole(listener = ConsoleListener())
+ pconsole = SimConsole()
puart0 = Uart8250(pio_addr=0x1f10000000)
# Attach I/O devices to specified bus object. Can't do this