Move SimObject python files alongside the C++ and fix

the SConscript files so that only the objects that are
actually available in a given build are compiled in.
Remove a bunch of files that aren't used anymore.

--HG--
rename : src/python/m5/objects/AlphaTLB.py => src/arch/alpha/AlphaTLB.py
rename : src/python/m5/objects/SparcTLB.py => src/arch/sparc/SparcTLB.py
rename : src/python/m5/objects/BaseCPU.py => src/cpu/BaseCPU.py
rename : src/python/m5/objects/FuncUnit.py => src/cpu/FuncUnit.py
rename : src/python/m5/objects/IntrControl.py => src/cpu/IntrControl.py
rename : src/python/m5/objects/MemTest.py => src/cpu/memtest/MemTest.py
rename : src/python/m5/objects/FUPool.py => src/cpu/o3/FUPool.py
rename : src/python/m5/objects/FuncUnitConfig.py => src/cpu/o3/FuncUnitConfig.py
rename : src/python/m5/objects/O3CPU.py => src/cpu/o3/O3CPU.py
rename : src/python/m5/objects/OzoneCPU.py => src/cpu/ozone/OzoneCPU.py
rename : src/python/m5/objects/SimpleOzoneCPU.py => src/cpu/ozone/SimpleOzoneCPU.py
rename : src/python/m5/objects/BadDevice.py => src/dev/BadDevice.py
rename : src/python/m5/objects/Device.py => src/dev/Device.py
rename : src/python/m5/objects/DiskImage.py => src/dev/DiskImage.py
rename : src/python/m5/objects/Ethernet.py => src/dev/Ethernet.py
rename : src/python/m5/objects/Ide.py => src/dev/Ide.py
rename : src/python/m5/objects/Pci.py => src/dev/Pci.py
rename : src/python/m5/objects/Platform.py => src/dev/Platform.py
rename : src/python/m5/objects/SimConsole.py => src/dev/SimConsole.py
rename : src/python/m5/objects/SimpleDisk.py => src/dev/SimpleDisk.py
rename : src/python/m5/objects/Uart.py => src/dev/Uart.py
rename : src/python/m5/objects/AlphaConsole.py => src/dev/alpha/AlphaConsole.py
rename : src/python/m5/objects/Tsunami.py => src/dev/alpha/Tsunami.py
rename : src/python/m5/objects/T1000.py => src/dev/sparc/T1000.py
rename : src/python/m5/objects/Bridge.py => src/mem/Bridge.py
rename : src/python/m5/objects/Bus.py => src/mem/Bus.py
rename : src/python/m5/objects/MemObject.py => src/mem/MemObject.py
rename : src/python/m5/objects/PhysicalMemory.py => src/mem/PhysicalMemory.py
rename : src/python/m5/objects/BaseCache.py => src/mem/cache/BaseCache.py
rename : src/python/m5/objects/CoherenceProtocol.py => src/mem/cache/coherence/CoherenceProtocol.py
rename : src/python/m5/objects/Repl.py => src/mem/cache/tags/Repl.py
rename : src/python/m5/objects/Process.py => src/sim/Process.py
rename : src/python/m5/objects/Root.py => src/sim/Root.py
rename : src/python/m5/objects/System.py => src/sim/System.py
extra : convert_revision : 173f8764bafa8ef899198438fa5573874e407321

1 files changed, 0 insertions, 95 deletions

diff --git a/src/python/m5/objects/Tsunami.py b/src/python/m5/objects/Tsunami.py
deleted file mode 100644
index 85105ff20..000000000
--- a/src/python/m5/objects/Tsunami.py
+++ /dev/null
@@ -1,95 +0,0 @@
-from m5.params import *
-from m5.proxy import *
-from Device import BasicPioDevice, IsaFake, BadAddr
-from Platform import Platform
-from AlphaConsole import AlphaConsole
-from Uart import Uart8250
-from Pci import PciConfigAll
-from BadDevice import BadDevice
-
-class TsunamiCChip(BasicPioDevice):
-    type = 'TsunamiCChip'
-    tsunami = Param.Tsunami(Parent.any, "Tsunami")
-
-class TsunamiIO(BasicPioDevice):
-    type = 'TsunamiIO'
-    time = Param.Time('01/01/2009',
-        "System time to use ('Now' for actual time)")
-    year_is_bcd = Param.Bool(False,
-        "The RTC should interpret the year as a BCD value")
-    tsunami = Param.Tsunami(Parent.any, "Tsunami")
-    frequency = Param.Frequency('1024Hz', "frequency of interrupts")
-
-class TsunamiPChip(BasicPioDevice):
-    type = 'TsunamiPChip'
-    tsunami = Param.Tsunami(Parent.any, "Tsunami")
-
-class Tsunami(Platform):
-    type = 'Tsunami'
-    system = Param.System(Parent.any, "system")
-
-    cchip = TsunamiCChip(pio_addr=0x801a0000000)
-    pchip = TsunamiPChip(pio_addr=0x80180000000)
-    pciconfig = PciConfigAll()
-    fake_sm_chip = IsaFake(pio_addr=0x801fc000370)
-
-    fake_uart1 = IsaFake(pio_addr=0x801fc0002f8)
-    fake_uart2 = IsaFake(pio_addr=0x801fc0003e8)
-    fake_uart3 = IsaFake(pio_addr=0x801fc0002e8)
-    fake_uart4 = IsaFake(pio_addr=0x801fc0003f0)
-
-    fake_ppc = IsaFake(pio_addr=0x801fc0003bb)
-
-    fake_OROM = IsaFake(pio_addr=0x800000a0000, pio_size=0x60000)
-
-    fake_pnp_addr = IsaFake(pio_addr=0x801fc000279)
-    fake_pnp_write = IsaFake(pio_addr=0x801fc000a79)
-    fake_pnp_read0 = IsaFake(pio_addr=0x801fc000203)
-    fake_pnp_read1 = IsaFake(pio_addr=0x801fc000243)
-    fake_pnp_read2 = IsaFake(pio_addr=0x801fc000283)
-    fake_pnp_read3 = IsaFake(pio_addr=0x801fc0002c3)
-    fake_pnp_read4 = IsaFake(pio_addr=0x801fc000303)
-    fake_pnp_read5 = IsaFake(pio_addr=0x801fc000343)
-    fake_pnp_read6 = IsaFake(pio_addr=0x801fc000383)
-    fake_pnp_read7 = IsaFake(pio_addr=0x801fc0003c3)
-
-    fake_ata0 = IsaFake(pio_addr=0x801fc0001f0)
-    fake_ata1 = IsaFake(pio_addr=0x801fc000170)
-
-    fb = BadDevice(pio_addr=0x801fc0003d0, devicename='FrameBuffer')
-    io = TsunamiIO(pio_addr=0x801fc000000)
-    uart = Uart8250(pio_addr=0x801fc0003f8)
-    console = AlphaConsole(pio_addr=0x80200000000, disk=Parent.simple_disk)
-
-    # Attach I/O devices to specified bus object.  Can't do this
-    # earlier, since the bus object itself is typically defined at the
-    # System level.
-    def attachIO(self, bus):
-        self.cchip.pio = bus.port
-        self.pchip.pio = bus.port
-        self.pciconfig.pio = bus.default
-        bus.responder_set = True
-        bus.responder = self.pciconfig
-        self.fake_sm_chip.pio = bus.port
-        self.fake_uart1.pio = bus.port
-        self.fake_uart2.pio = bus.port
-        self.fake_uart3.pio = bus.port
-        self.fake_uart4.pio = bus.port
-        self.fake_ppc.pio = bus.port
-        self.fake_OROM.pio = bus.port
-        self.fake_pnp_addr.pio = bus.port
-        self.fake_pnp_write.pio = bus.port
-        self.fake_pnp_read0.pio = bus.port
-        self.fake_pnp_read1.pio = bus.port
-        self.fake_pnp_read2.pio = bus.port
-        self.fake_pnp_read3.pio = bus.port
-        self.fake_pnp_read4.pio = bus.port
-        self.fake_pnp_read5.pio = bus.port
-        self.fake_pnp_read6.pio = bus.port
-        self.fake_pnp_read7.pio = bus.port
-        self.fake_ata0.pio = bus.port
-        self.fake_ata1.pio = bus.port
-        self.fb.pio = bus.port
-        self.io.pio = bus.port
-        self.uart.pio = bus.port
-        self.console.pio = bus.port