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| author | Kevin Lim <ktlim@umich.edu> | 2006-11-02 15:20:37 -0500 |
|---|---|---|
| committer | Kevin Lim <ktlim@umich.edu> | 2006-11-02 15:20:37 -0500 |
| commit | 45363ea658251df0c31a75d7bd5d0ac3a3809623 (patch) | |
| tree | bae91271cf1e57d6cacbf0bbe4853f0db0067797 /src/python/m5/objects/Tsunami.py | |
| parent | c3485a654888f641dca23128f8197ef747c706d2 (diff) | |
| download | gem5-45363ea658251df0c31a75d7bd5d0ac3a3809623.tar.xz | |
Have bus use the BadAddress device to handle bad addresses. The O3 CPU should be able to boot into Linux with caches on after this change.
src/mem/bus.cc:
src/mem/bus.hh:
Bus now will be setup with a default responder, unless the user overrides it. This default responder should return BadAddress if no matching port is found.
src/python/m5/objects/Bus.py:
Bus now has a default responder for FS mode if the user doesn't override it. It returns BadAddress if no matching port is found.
src/python/m5/objects/Tsunami.py:
Add bad address device. Also record when the user has specified their own default responder.
--HG--
extra : convert_revision : 59070477ae313ee711b2d59baa2369c9a91c5b85
Diffstat (limited to 'src/python/m5/objects/Tsunami.py')
| -rw-r--r-- | src/python/m5/objects/Tsunami.py | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/python/m5/objects/Tsunami.py b/src/python/m5/objects/Tsunami.py index 0b53153a0..42bcab089 100644 --- a/src/python/m5/objects/Tsunami.py +++ b/src/python/m5/objects/Tsunami.py @@ -15,6 +15,9 @@ class IsaFake(BasicPioDevice): type = 'IsaFake' pio_size = Param.Addr(0x8, "Size of address range") +class BadAddr(BasicPioDevice): + type = 'BadAddr' + class TsunamiIO(BasicPioDevice): type = 'TsunamiIO' time = Param.UInt64(1136073600, @@ -70,6 +73,7 @@ class Tsunami(Platform): self.cchip.pio = bus.port self.pchip.pio = bus.port self.pciconfig.pio = bus.default + bus.responder_set = True self.fake_sm_chip.pio = bus.port self.fake_uart1.pio = bus.port self.fake_uart2.pio = bus.port |