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authorAli Saidi <saidi@eecs.umich.edu>2006-07-06 14:41:09 -0400
committerAli Saidi <saidi@eecs.umich.edu>2006-07-06 14:41:09 -0400
commit4b741100714c6f20749f344ddd4b16459f28df72 (patch)
tree613d4bf11ced3c8df4b5bb2e9a68a3df04b11333 /src/python/m5/objects
parente60f998e2993df35460c8835016b3043a13da80a (diff)
parent93839380e7dc4799d234843d10329c03d38487fa (diff)
downloadgem5-4b741100714c6f20749f344ddd4b16459f28df72.tar.xz
Merge zizzer:/bk/newmem
into zeep.pool:/z/saidi/work/m5.newmem --HG-- extra : convert_revision : 4669e87d29fa3e0ca9009f6b9dce72113220d7bc
Diffstat (limited to 'src/python/m5/objects')
-rw-r--r--src/python/m5/objects/Bus.py1
-rw-r--r--src/python/m5/objects/Pci.py10
2 files changed, 8 insertions, 3 deletions
diff --git a/src/python/m5/objects/Bus.py b/src/python/m5/objects/Bus.py
index 019e15034..e0278e6c3 100644
--- a/src/python/m5/objects/Bus.py
+++ b/src/python/m5/objects/Bus.py
@@ -4,4 +4,5 @@ from MemObject import MemObject
class Bus(MemObject):
type = 'Bus'
port = VectorPort("vector port for connecting devices")
+ default = Port("Default port for requests that aren't handeled by a device.")
bus_id = Param.Int(0, "blah")
diff --git a/src/python/m5/objects/Pci.py b/src/python/m5/objects/Pci.py
index 9e1e91b13..29014bb37 100644
--- a/src/python/m5/objects/Pci.py
+++ b/src/python/m5/objects/Pci.py
@@ -1,5 +1,5 @@
from m5.config import *
-from Device import BasicPioDevice, DmaDevice
+from Device import BasicPioDevice, DmaDevice, PioDevice
class PciConfigData(SimObject):
type = 'PciConfigData'
@@ -38,18 +38,22 @@ class PciConfigData(SimObject):
MaximumLatency = Param.UInt8(0x00, "Maximum Latency")
MinimumGrant = Param.UInt8(0x00, "Minimum Grant")
-class PciConfigAll(BasicPioDevice):
+class PciConfigAll(PioDevice):
type = 'PciConfigAll'
+ pio_latency = Param.Tick(1, "Programmed IO latency in simticks")
+ bus = Param.UInt8(0x00, "PCI bus to act as config space for")
+ size = Param.MemorySize32('16MB', "Size of config space")
+
class PciDevice(DmaDevice):
type = 'PciDevice'
abstract = True
+ config = Port("PCI configuration space port")
pci_bus = Param.Int("PCI bus")
pci_dev = Param.Int("PCI device number")
pci_func = Param.Int("PCI function code")
pio_latency = Param.Tick(1, "Programmed IO latency in simticks")
configdata = Param.PciConfigData(Parent.any, "PCI Config data")
- configspace = Param.PciConfigAll(Parent.any, "PCI Configspace")
class PciFake(PciDevice):
type = 'PciFake'