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authorKevin Lim <ktlim@umich.edu>2006-07-07 17:33:24 -0400
committerKevin Lim <ktlim@umich.edu>2006-07-07 17:33:24 -0400
commit8ade33d324218737c815935120307153975eeadc (patch)
tree587a5dce799c0f5a2901dd1eaf452b2ae1ccfbc5 /src/python/m5/objects
parent744e0055b704f4c202e765f46e4fd4f56e1b847c (diff)
downloadgem5-8ade33d324218737c815935120307153975eeadc.tar.xz
Support Ron's changes for hooking up ports.
src/cpu/checker/cpu.hh: Now that BaseCPU is a MemObject, the checker must define this function. src/cpu/o3/cpu.cc: src/cpu/o3/cpu.hh: src/cpu/o3/fetch.hh: src/cpu/o3/iew.hh: src/cpu/o3/lsq.hh: src/cpu/o3/lsq_unit.hh: Implement getPort function so the connector can connect the ports properly. src/cpu/o3/fetch_impl.hh: src/cpu/o3/lsq_unit_impl.hh: The connector handles connecting the ports now. src/python/m5/objects/O3CPU.py: Add ports to the parameters. --HG-- extra : convert_revision : 0b1a216b9a5d0574e62165d7c6c242498104d918
Diffstat (limited to 'src/python/m5/objects')
-rw-r--r--src/python/m5/objects/O3CPU.py2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/python/m5/objects/O3CPU.py b/src/python/m5/objects/O3CPU.py
index 9ccbdcf53..6ba62b47e 100644
--- a/src/python/m5/objects/O3CPU.py
+++ b/src/python/m5/objects/O3CPU.py
@@ -10,6 +10,8 @@ class DerivO3CPU(BaseCPU):
checker = Param.BaseCPU(NULL, "checker")
cachePorts = Param.Unsigned("Cache Ports")
+ icache_port = Port("Instruction Port")
+ dcache_port = Port("Data Port")
decodeToFetchDelay = Param.Unsigned("Decode to fetch delay")
renameToFetchDelay = Param.Unsigned("Rename to fetch delay")