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| author | Nathan Binkert <binkertn@umich.edu> | 2007-03-06 11:13:43 -0800 |
|---|---|---|
| committer | Nathan Binkert <binkertn@umich.edu> | 2007-03-06 11:13:43 -0800 |
| commit | d55b25cde6d2c072885a2c468d209fb18d6628e6 (patch) | |
| tree | 391c4e66a69818a95037a5f2adccb2e8e0c84648 /src/python/m5/objects | |
| parent | f800fddcea850822efee031b9b904280639da4c6 (diff) | |
| download | gem5-d55b25cde6d2c072885a2c468d209fb18d6628e6.tar.xz | |
Move all of the parameters of the Root SimObject so they are
directly configured by python. Move stuff from root.(cc|hh) to
core.(cc|hh) since it really belogs there now.
In the process, simplify how ticks are used in the python code.
--HG--
extra : convert_revision : cf82ee1ea20f9343924f30bacc2a38d4edee8df3
Diffstat (limited to 'src/python/m5/objects')
| -rw-r--r-- | src/python/m5/objects/BaseCPU.py | 4 | ||||
| -rw-r--r-- | src/python/m5/objects/PhysicalMemory.py | 2 | ||||
| -rw-r--r-- | src/python/m5/objects/Root.py | 7 |
3 files changed, 4 insertions, 9 deletions
diff --git a/src/python/m5/objects/BaseCPU.py b/src/python/m5/objects/BaseCPU.py index 67a28a61e..986220c3f 100644 --- a/src/python/m5/objects/BaseCPU.py +++ b/src/python/m5/objects/BaseCPU.py @@ -47,8 +47,8 @@ class BaseCPU(SimObject): defer_registration = Param.Bool(False, "defer registration with system (for sampling)") - clock = Param.Clock(Parent.clock, "clock speed") - phase = Param.Latency("0ns", "clock phase") + clock = Param.Clock('1t', "clock speed") + phase = Param.Latency('0ns', "clock phase") _mem_ports = [] diff --git a/src/python/m5/objects/PhysicalMemory.py b/src/python/m5/objects/PhysicalMemory.py index b8df6229e..c389e4a7f 100644 --- a/src/python/m5/objects/PhysicalMemory.py +++ b/src/python/m5/objects/PhysicalMemory.py @@ -8,7 +8,7 @@ class PhysicalMemory(MemObject): functional = Port("Functional Access Port") range = Param.AddrRange(AddrRange('128MB'), "Device Address") file = Param.String('', "memory mapped file") - latency = Param.Latency(Parent.clock, "latency of an access") + latency = Param.Latency('1t', "latency of an access") zero = Param.Bool(False, "zero initialize memory") class DRAMMemory(PhysicalMemory): diff --git a/src/python/m5/objects/Root.py b/src/python/m5/objects/Root.py index 8db4fa5a2..2b0e736e7 100644 --- a/src/python/m5/objects/Root.py +++ b/src/python/m5/objects/Root.py @@ -3,9 +3,4 @@ from m5.params import * class Root(SimObject): type = 'Root' - clock = Param.RootClock('1THz', "tick frequency") - max_tick = Param.Tick('0', "maximum simulation ticks (0 = infinite)") - progress_interval = Param.Tick('0', - "print a progress message every n ticks (0 = never)") - output_file = Param.String('cout', "file to dump simulator output to") - checkpoint = Param.String('', "checkpoint file to load") + dummy = Param.Int(0, "We don't support objects without params") |