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| author | Kevin Lim <ktlim@umich.edu> | 2006-07-27 16:43:02 -0400 |
|---|---|---|
| committer | Kevin Lim <ktlim@umich.edu> | 2006-07-27 16:43:02 -0400 |
| commit | 64b72130463f217bc2ce3e592630406e9f832d16 (patch) | |
| tree | 4576e05f9f2e9305bfafbd6e212a403754f434b7 /src/python/m5/objects | |
| parent | f9729e999f71895f6b53f8189bdff535e7c7b70e (diff) | |
| download | gem5-64b72130463f217bc2ce3e592630406e9f832d16.tar.xz | |
Need config read/write latency.
--HG--
extra : convert_revision : 2d978635db89e727f228890738b24fcad9b6ced6
Diffstat (limited to 'src/python/m5/objects')
| -rw-r--r-- | src/python/m5/objects/Ethernet.py | 2 | ||||
| -rw-r--r-- | src/python/m5/objects/Ide.py | 2 |
2 files changed, 4 insertions, 0 deletions
diff --git a/src/python/m5/objects/Ethernet.py b/src/python/m5/objects/Ethernet.py index db7efe004..fb641bf80 100644 --- a/src/python/m5/objects/Ethernet.py +++ b/src/python/m5/objects/Ethernet.py @@ -68,6 +68,8 @@ class EtherDevBase(PciDevice): clock = Param.Clock('0ns', "State machine processor frequency") + config_latency = Param.Latency('20ns', "Config read or write latency") + dma_read_delay = Param.Latency('0us', "fixed delay for dma reads") dma_read_factor = Param.Latency('0us', "multiplier for dma reads") dma_write_delay = Param.Latency('0us', "fixed delay for dma writes") diff --git a/src/python/m5/objects/Ide.py b/src/python/m5/objects/Ide.py index a5fe1b595..a8bd4ac5a 100644 --- a/src/python/m5/objects/Ide.py +++ b/src/python/m5/objects/Ide.py @@ -36,4 +36,6 @@ class IdeController(PciDevice): type = 'IdeController' disks = VectorParam.IdeDisk("IDE disks attached to this controller") + config_latency = Param.Latency('20ns', "Config read or write latency") + configdata =IdeControllerPciData() |