More changes to get SPARC fs closer. Now at 1.2M cycles before difference

configs/common/FSConfig.py:
    seperate the hypervisor memory and the guest0 memory. In reality we're going to need a better way to do this at some point. Perhaps auto generating the hv-desc image based on the specified config.
src/arch/sparc/isa/decoder.isa:
    change reads/writes to the [hs]tick(cmpr) registers to use readmiscregwitheffect
src/arch/sparc/miscregfile.cc:
    For niagra stick and tick are aliased to one value (if we end up doing mps we might not want this).
    Use instruction count from cpu rather than cycles because that is what legion does
    we can change it back after were done with legion
src/base/bitfield.hh:
    add a new function mbits() that just masks off bits of interest but doesn't shift
src/cpu/base.cc:
src/cpu/base.hh:
    add instruction count to cpu
src/cpu/exetrace.cc:
src/cpu/m5legion_interface.h:
    compare instruction count between legion and m5 too
src/cpu/simple/atomic.cc:
    change asserts of packet success to if panics wrapped with NDEBUG defines
    so we can get some more useful information when we have a bad address
src/dev/isa_fake.cc:
src/dev/isa_fake.hh:
src/python/m5/objects/Device.py:
    expand isa fake a bit more having data for each size request, the ability to have writes update the data and to warn on accesses
src/python/m5/objects/System.py:
    convert some tabs to spaces
src/python/m5/objects/T1000.py:
    add more fake devices for each l1 bank and each memory controller

--HG--
extra : convert_revision : 8024ae07b765a04ff6f600e5875b55d8a7d3d276

2 files changed, 49 insertions, 4 deletions

diff --git a/src/python/m5/objects/Device.py b/src/python/m5/objects/Device.py
index 9a3c258de..f4b873a60 100644
--- a/src/python/m5/objects/Device.py
+++ b/src/python/m5/objects/Device.py
@@ -23,8 +23,13 @@ class DmaDevice(PioDevice):
 class IsaFake(BasicPioDevice):
     type = 'IsaFake'
     pio_size = Param.Addr(0x8, "Size of address range")
-    ret_data = Param.UInt8(0xFF, "Default data to return")
+    ret_data8 = Param.UInt8(0xFF, "Default data to return")
+    ret_data16 = Param.UInt16(0xFFFF, "Default data to return")
+    ret_data32 = Param.UInt32(0xFFFFFFFF, "Default data to return")
+    ret_data64 = Param.UInt64(0xFFFFFFFFFFFFFFFF, "Default data to return")
     ret_bad_addr = Param.Bool(False, "Return pkt status bad address on access")
+    update_data = Param.Bool(False, "Update the data that is returned on writes")
+    warn_access = Param.String("", "String to print when device is accessed")
 
 class BadAddr(IsaFake):
     ret_bad_addr = Param.Bool(True, "Return pkt status bad address on access")
diff --git a/src/python/m5/objects/T1000.py b/src/python/m5/objects/T1000.py
index 235171a51..f4ec5bec4 100644
--- a/src/python/m5/objects/T1000.py
+++ b/src/python/m5/objects/T1000.py
@@ -9,14 +9,54 @@ class T1000(Platform):
     type = 'T1000'
     system = Param.System(Parent.any, "system")
 
-    fake_iob = IsaFake(pio_addr=0x8000000000, pio_size=0x7F00000000)
+    fake_clk = IsaFake(pio_addr=0x9600000000, pio_size=0x100000000,
+            warn_access="Accessing Clock Unit -- Unimplemented!")
 
-    uart = Uart8250(pio_addr=0xfff0c2c000)
+    fake_membnks = IsaFake(pio_addr=0x9700000000, pio_size=16384,
+            ret_data64=0x0000000000000000, update_data=False,
+            warn_access="Accessing Memory Banks -- Unimplemented!")
+
+    fake_iob = IsaFake(pio_addr=0x9800000000, pio_size=0x100000000,
+            warn_access="Accessing IOB -- Unimplemented!")
+
+    fake_jbi = IsaFake(pio_addr=0x8000000000, pio_size=0x100000000,
+            warn_access="Accessing JBI -- Unimplemented!")
+
+    fake_l2_1 = IsaFake(pio_addr=0xA900000000, pio_size=0x8,
+            ret_data64=0x0000000000000001, update_data=True,
+            warn_access="Accessing L2 Cache Banks -- Unimplemented!")
+
+    fake_l2_2 = IsaFake(pio_addr=0xA900000040, pio_size=0x8,
+            ret_data64=0x0000000000000001, update_data=True,
+            warn_access="Accessing L2 Cache Banks -- Unimplemented!")
+
+    fake_l2_3 = IsaFake(pio_addr=0xA900000080, pio_size=0x8,
+            ret_data64=0x0000000000000001, update_data=True,
+            warn_access="Accessing L2 Cache Banks -- Unimplemented!")
+
+    fake_l2_4 = IsaFake(pio_addr=0xA9000000C0, pio_size=0x8,
+            ret_data64=0x0000000000000001, update_data=True,
+            warn_access="Accessing L2 Cache Banks -- Unimplemented!")
+
+    fake_ssi = IsaFake(pio_addr=0xff00000000, pio_size=0x10000000,
+            warn_access="Accessing SSI -- Unimplemented!")
+
+    hvuart = Uart8250(pio_addr=0xfff0c2c000)
+    puart0 = Uart8250(pio_addr=0x1f10000000)
     console = SimConsole(listener = ConsoleListener())
 
     # Attach I/O devices to specified bus object.  Can't do this
     # earlier, since the bus object itself is typically defined at the
     # System level.
     def attachIO(self, bus):
+        self.fake_clk.pio = bus.port
+        self.fake_membnks.pio = bus.port
         self.fake_iob.pio = bus.port
-        self.uart.pio = bus.port
+        self.fake_jbi.pio = bus.port
+        self.fake_l2_1.pio = bus.port
+        self.fake_l2_2.pio = bus.port
+        self.fake_l2_3.pio = bus.port
+        self.fake_l2_4.pio = bus.port
+        self.fake_ssi.pio = bus.port
+        self.puart0.pio = bus.port
+        self.hvuart.pio = bus.port