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| author | Ali Saidi <saidi@eecs.umich.edu> | 2007-05-13 04:48:42 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-05-13 04:48:42 -0400 |
| commit | 404a91265efbf1a039fe1e19a8c1d8ff86a904b1 (patch) | |
| tree | 3d4c5f1d882fa0c521acf273e8d00fd2a3abdd46 /src/python/m5/objects | |
| parent | 376cff64bd3ac5bafd8fa566674964fd4836790c (diff) | |
| parent | 011db5c8515804145202373440bad26fa21b30a7 (diff) | |
| download | gem5-404a91265efbf1a039fe1e19a8c1d8ff86a904b1.tar.xz | |
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into zizzer.eecs.umich.edu:/tmp/newmem
--HG--
extra : convert_revision : 162876cb1ad96ca7ca6a2e0f549c98b29e5a8d2d
Diffstat (limited to 'src/python/m5/objects')
| -rw-r--r-- | src/python/m5/objects/BaseCache.py | 3 | ||||
| -rw-r--r-- | src/python/m5/objects/Bridge.py | 7 | ||||
| -rw-r--r-- | src/python/m5/objects/Device.py | 6 |
3 files changed, 12 insertions, 4 deletions
diff --git a/src/python/m5/objects/BaseCache.py b/src/python/m5/objects/BaseCache.py index 773a11bea..7df5215e4 100644 --- a/src/python/m5/objects/BaseCache.py +++ b/src/python/m5/objects/BaseCache.py @@ -9,7 +9,7 @@ class BaseCache(MemObject): "Use an adaptive compression scheme") assoc = Param.Int("associativity") block_size = Param.Int("block size in bytes") - latency = Param.Int("Latency") + latency = Param.Latency("Latency") compressed_bus = Param.Bool(False, "This cache connects to a compressed memory") compression_latency = Param.Latency('0ns', @@ -59,6 +59,5 @@ class BaseCache(MemObject): "Use the CPU ID to seperate calculations of prefetches") prefetch_data_accesses_only = Param.Bool(False, "Only prefetch on data not on instruction accesses") - hit_latency = Param.Int(1,"Hit Latency of the cache") cpu_side = Port("Port on side closer to CPU") mem_side = Port("Port on side closer to MEM") diff --git a/src/python/m5/objects/Bridge.py b/src/python/m5/objects/Bridge.py index e123c2891..33b24ad3c 100644 --- a/src/python/m5/objects/Bridge.py +++ b/src/python/m5/objects/Bridge.py @@ -5,9 +5,12 @@ class Bridge(MemObject): type = 'Bridge' side_a = Port('Side A port') side_b = Port('Side B port') - queue_size_a = Param.Int(16, "The number of requests to buffer") - queue_size_b = Param.Int(16, "The number of requests to buffer") + req_size_a = Param.Int(16, "The number of requests to buffer") + req_size_b = Param.Int(16, "The number of requests to buffer") + resp_size_a = Param.Int(16, "The number of requests to buffer") + resp_size_b = Param.Int(16, "The number of requests to buffer") delay = Param.Latency('0ns', "The latency of this bridge") + nack_delay = Param.Latency('0ns', "The latency of this bridge") write_ack = Param.Bool(False, "Should this bridge ack writes") fix_partial_write_a = Param.Bool(False, "Should this bridge fixup partial block writes") fix_partial_write_b = Param.Bool(False, "Should this bridge fixup partial block writes") diff --git a/src/python/m5/objects/Device.py b/src/python/m5/objects/Device.py index f4b873a60..90fbfb552 100644 --- a/src/python/m5/objects/Device.py +++ b/src/python/m5/objects/Device.py @@ -19,6 +19,12 @@ class DmaDevice(PioDevice): type = 'DmaDevice' abstract = True dma = Port(Self.pio.peerObj.port, "DMA port") + min_backoff_delay = Param.Latency('4ns', + "min time between a nack packet being received and the next request made by the device") + max_backoff_delay = Param.Latency('10us', + "max time between a nack packet being received and the next request made by the device") + + class IsaFake(BasicPioDevice): type = 'IsaFake' |