Merge m5.eecs.umich.edu:/bk/newmem

into  ewok.(none):/home/gblack/m5/newmem

--HG--
extra : convert_revision : 516c357f98c7a571c70362babd3fa162fbc2ed5a

11 files changed, 54 insertions, 20 deletions

diff --git a/src/python/m5/objects/BaseCPU.py b/src/python/m5/objects/BaseCPU.py
index 2e78578df..5bf98be9c 100644
--- a/src/python/m5/objects/BaseCPU.py
+++ b/src/python/m5/objects/BaseCPU.py
@@ -6,10 +6,10 @@ class BaseCPU(SimObject):
     abstract = True
     mem = Param.MemObject("memory")
 
+    system = Param.System(Parent.any, "system object")
     if build_env['FULL_SYSTEM']:
         dtb = Param.AlphaDTB("Data TLB")
         itb = Param.AlphaITB("Instruction TLB")
-        system = Param.System(Parent.any, "system object")
         cpu_id = Param.Int(-1, "CPU identifier")
     else:
         workload = VectorParam.Process("processes to run")
diff --git a/src/python/m5/objects/BaseCache.py b/src/python/m5/objects/BaseCache.py
index 33f44759b..497b2b038 100644
--- a/src/python/m5/objects/BaseCache.py
+++ b/src/python/m5/objects/BaseCache.py
@@ -1,29 +1,26 @@
 from m5.config import *
-from BaseMem import BaseMem
+from MemObject import MemObject
 
 class Prefetch(Enum): vals = ['none', 'tagged', 'stride', 'ghb']
 
-class BaseCache(BaseMem):
+class BaseCache(MemObject):
     type = 'BaseCache'
     adaptive_compression = Param.Bool(False,
         "Use an adaptive compression scheme")
     assoc = Param.Int("associativity")
     block_size = Param.Int("block size in bytes")
+    latency = Param.Int("Latency")
     compressed_bus = Param.Bool(False,
         "This cache connects to a compressed memory")
     compression_latency = Param.Latency('0ns',
         "Latency in cycles of compression algorithm")
     do_copy = Param.Bool(False, "perform fast copies in the cache")
     hash_delay = Param.Int(1, "time in cycles of hash access")
-    in_bus = Param.Bus(NULL, "incoming bus object")
     lifo = Param.Bool(False,
         "whether this NIC partition should use LIFO repl. policy")
     max_miss_count = Param.Counter(0,
         "number of misses to handle before calling exit")
-    mem_trace = Param.MemTraceWriter(NULL,
-                                     "memory trace writer to record accesses")
     mshrs = Param.Int("number of MSHRs (max outstanding requests)")
-    out_bus = Param.Bus("outgoing bus object")
     prioritizeRequests = Param.Bool(False,
         "always service demand misses first")
     protocol = Param.CoherenceProtocol(NULL, "coherence protocol to use")
@@ -63,3 +60,6 @@ class BaseCache(BaseMem):
          "Use the CPU ID to seperate calculations of prefetches")
     prefetch_data_accesses_only = Param.Bool(False,
          "Only prefetch on data not on instruction accesses")
+    hit_latency = Param.Int(1,"Hit Latency of the cache")
+    cpu_side = Port("Port on side closer to CPU")
+    mem_side = Port("Port on side closer to MEM")
diff --git a/src/python/m5/objects/Bridge.py b/src/python/m5/objects/Bridge.py
index 880535755..c9e673afb 100644
--- a/src/python/m5/objects/Bridge.py
+++ b/src/python/m5/objects/Bridge.py
@@ -3,6 +3,8 @@ from MemObject import MemObject
 
 class Bridge(MemObject):
     type = 'Bridge'
+    side_a = Port('Side A port')
+    side_b = Port('Side B port')
     queue_size_a = Param.Int(16, "The number of requests to buffer")
     queue_size_b = Param.Int(16, "The number of requests to buffer")
     delay = Param.Latency('0ns', "The latency of this bridge")
diff --git a/src/python/m5/objects/Bus.py b/src/python/m5/objects/Bus.py
index c37dab438..e0278e6c3 100644
--- a/src/python/m5/objects/Bus.py
+++ b/src/python/m5/objects/Bus.py
@@ -3,4 +3,6 @@ from MemObject import MemObject
 
 class Bus(MemObject):
     type = 'Bus'
+    port = VectorPort("vector port for connecting devices")
+    default = Port("Default port for requests that aren't handeled by a device.")
     bus_id = Param.Int(0, "blah")
diff --git a/src/python/m5/objects/Device.py b/src/python/m5/objects/Device.py
index 7798f5f04..222f750da 100644
--- a/src/python/m5/objects/Device.py
+++ b/src/python/m5/objects/Device.py
@@ -4,6 +4,7 @@ from MemObject import MemObject
 class PioDevice(MemObject):
     type = 'PioDevice'
     abstract = True
+    pio = Port("Programmed I/O port")
     platform = Param.Platform(Parent.any, "Platform this device is part of")
     system = Param.System(Parent.any, "System this device is part of")
 
@@ -16,3 +17,4 @@ class BasicPioDevice(PioDevice):
 class DmaDevice(PioDevice):
     type = 'DmaDevice'
     abstract = True
+    dma = Port("DMA port")
diff --git a/src/python/m5/objects/FuncUnit.py b/src/python/m5/objects/FuncUnit.py
new file mode 100644
index 000000000..f61590ae9
--- /dev/null
+++ b/src/python/m5/objects/FuncUnit.py
@@ -0,0 +1,17 @@
+from m5.config import *
+
+class OpType(Enum):
+    vals = ['(null)', 'IntAlu', 'IntMult', 'IntDiv', 'FloatAdd',
+            'FloatCmp', 'FloatCvt', 'FloatMult', 'FloatDiv', 'FloatSqrt',
+            'MemRead', 'MemWrite', 'IprAccess', 'InstPrefetch']
+
+class OpDesc(SimObject):
+    type = 'OpDesc'
+    issueLat = Param.Int(1, "cycles until another can be issued")
+    opClass = Param.OpType("type of operation")
+    opLat = Param.Int(1, "cycles until result is available")
+
+class FUDesc(SimObject):
+    type = 'FUDesc'
+    count = Param.Int("number of these FU's available")
+    opList = VectorParam.OpDesc("operation classes for this FU type")
diff --git a/src/python/m5/objects/AlphaFullCPU.py b/src/python/m5/objects/O3CPU.py
index 2988305d3..d6bc454ad 100644
--- a/src/python/m5/objects/AlphaFullCPU.py
+++ b/src/python/m5/objects/O3CPU.py
@@ -2,14 +2,16 @@ from m5 import build_env
 from m5.config import *
 from BaseCPU import BaseCPU
 
-class DerivAlphaFullCPU(BaseCPU):
-    type = 'DerivAlphaFullCPU'
+class DerivO3CPU(BaseCPU):
+    type = 'DerivO3CPU'
     activity = Param.Unsigned("Initial count")
     numThreads = Param.Unsigned("number of HW thread contexts")
 
     checker = Param.BaseCPU(NULL, "checker")
 
     cachePorts = Param.Unsigned("Cache Ports")
+    icache_port = Port("Instruction Port")
+    dcache_port = Port("Data Port")
 
     decodeToFetchDelay = Param.Unsigned("Decode to fetch delay")
     renameToFetchDelay = Param.Unsigned("Rename to fetch delay")
@@ -37,12 +39,10 @@ class DerivAlphaFullCPU(BaseCPU):
                "Issue/Execute/Writeback delay")
     issueToExecuteDelay = Param.Unsigned("Issue to execute delay (internal "
               "to the IEW stage)")
+    dispatchWidth = Param.Unsigned("Dispatch width")
     issueWidth = Param.Unsigned("Issue width")
-    executeWidth = Param.Unsigned("Execute width")
-    executeIntWidth = Param.Unsigned("Integer execute width")
-    executeFloatWidth = Param.Unsigned("Floating point execute width")
-    executeBranchWidth = Param.Unsigned("Branch execute width")
-    executeMemoryWidth = Param.Unsigned("Memory execute width")
+    wbWidth = Param.Unsigned("Writeback width")
+    wbDepth = Param.Unsigned("Writeback depth")
     fuPool = Param.FUPool(NULL, "Functional Unit pool")
 
     iewToCommitDelay = Param.Unsigned("Issue/Execute/Writeback to commit "
@@ -53,6 +53,9 @@ class DerivAlphaFullCPU(BaseCPU):
     trapLatency = Param.Tick("Trap latency")
     fetchTrapLatency = Param.Tick("Fetch trap latency")
 
+    backComSize = Param.Unsigned("Time buffer size for backwards communication")
+    forwardComSize = Param.Unsigned("Time buffer size for forward communication")
+
     predType = Param.String("Branch predictor type ('local', 'tournament')")
     localPredictorSize = Param.Unsigned("Size of local predictor")
     localCtrBits = Param.Unsigned("Bits per counter")
diff --git a/src/python/m5/objects/OzoneCPU.py b/src/python/m5/objects/OzoneCPU.py
index f2d9aea84..88fb63c74 100644
--- a/src/python/m5/objects/OzoneCPU.py
+++ b/src/python/m5/objects/OzoneCPU.py
@@ -7,11 +7,11 @@ class DerivOzoneCPU(BaseCPU):
 
     numThreads = Param.Unsigned("number of HW thread contexts")
 
-    if not build_env['FULL_SYSTEM']:
-        mem = Param.FunctionalMemory(NULL, "memory")
-
     checker = Param.BaseCPU("Checker CPU")
 
+    icache_port = Port("Instruction Port")
+    dcache_port = Port("Data Port")
+
     width = Param.Unsigned("Width")
     frontEndWidth = Param.Unsigned("Front end width")
     backEndWidth = Param.Unsigned("Back end width")
diff --git a/src/python/m5/objects/Pci.py b/src/python/m5/objects/Pci.py
index 9e1e91b13..29014bb37 100644
--- a/src/python/m5/objects/Pci.py
+++ b/src/python/m5/objects/Pci.py
@@ -1,5 +1,5 @@
 from m5.config import *
-from Device import BasicPioDevice, DmaDevice
+from Device import BasicPioDevice, DmaDevice, PioDevice
 
 class PciConfigData(SimObject):
     type = 'PciConfigData'
@@ -38,18 +38,22 @@ class PciConfigData(SimObject):
     MaximumLatency = Param.UInt8(0x00, "Maximum Latency")
     MinimumGrant = Param.UInt8(0x00, "Minimum Grant")
 
-class PciConfigAll(BasicPioDevice):
+class PciConfigAll(PioDevice):
     type = 'PciConfigAll'
+    pio_latency = Param.Tick(1, "Programmed IO latency in simticks")
+    bus = Param.UInt8(0x00, "PCI bus to act as config space for")
+    size = Param.MemorySize32('16MB', "Size of config space")
+
 
 class PciDevice(DmaDevice):
     type = 'PciDevice'
     abstract = True
+    config = Port("PCI configuration space port")
     pci_bus = Param.Int("PCI bus")
     pci_dev = Param.Int("PCI device number")
     pci_func = Param.Int("PCI function code")
     pio_latency = Param.Tick(1, "Programmed IO latency in simticks")
     configdata = Param.PciConfigData(Parent.any, "PCI Config data")
-    configspace = Param.PciConfigAll(Parent.any, "PCI Configspace")
 
 class PciFake(PciDevice):
     type = 'PciFake'
diff --git a/src/python/m5/objects/PhysicalMemory.py b/src/python/m5/objects/PhysicalMemory.py
index bed90d555..9cc7510a2 100644
--- a/src/python/m5/objects/PhysicalMemory.py
+++ b/src/python/m5/objects/PhysicalMemory.py
@@ -3,6 +3,7 @@ from MemObject import *
 
 class PhysicalMemory(MemObject):
     type = 'PhysicalMemory'
+    port = Port("the access port")
     range = Param.AddrRange("Device Address")
     file = Param.String('', "memory mapped file")
     latency = Param.Latency(Parent.clock, "latency of an access")
diff --git a/src/python/m5/objects/System.py b/src/python/m5/objects/System.py
index 9a1e1d690..386f39277 100644
--- a/src/python/m5/objects/System.py
+++ b/src/python/m5/objects/System.py
@@ -1,9 +1,12 @@
 from m5 import build_env
 from m5.config import *
 
+class MemoryMode(Enum): vals = ['invalid', 'atomic', 'timing']
+
 class System(SimObject):
     type = 'System'
     physmem = Param.PhysicalMemory(Parent.any, "phsyical memory")
+    mem_mode = Param.MemoryMode('atomic', "The mode the memory system is in")
     if build_env['FULL_SYSTEM']:
         boot_cpu_frequency = Param.Frequency(Self.cpu[0].clock.frequency,
                                              "boot processor frequency")