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authorKevin Lim <ktlim@umich.edu>2006-11-08 13:04:36 -0500
committerKevin Lim <ktlim@umich.edu>2006-11-08 13:04:36 -0500
commit344f72dd62f6cc9ab8c7ab5454a320b2e5674a37 (patch)
treedb6a77aa0efea4cc9815ce55e467d9d9877f6acf /src/python/m5/objects
parente174ec181508cc0a722a25d92ffc74c3038d44a1 (diff)
downloadgem5-344f72dd62f6cc9ab8c7ab5454a320b2e5674a37.tar.xz
Remove mem parameter. Should have been removed earlier.
src/python/m5/objects/BaseCPU.py: These parameters should have been removed in an earlier push. --HG-- extra : convert_revision : 781b39ca370361e9568b1af0be96ff5848b1f3f4
Diffstat (limited to 'src/python/m5/objects')
-rw-r--r--src/python/m5/objects/BaseCPU.py2
1 files changed, 0 insertions, 2 deletions
diff --git a/src/python/m5/objects/BaseCPU.py b/src/python/m5/objects/BaseCPU.py
index b6dc08e46..4e34e8a4e 100644
--- a/src/python/m5/objects/BaseCPU.py
+++ b/src/python/m5/objects/BaseCPU.py
@@ -8,7 +8,6 @@ from Bus import Bus
class BaseCPU(SimObject):
type = 'BaseCPU'
abstract = True
- mem = Param.MemObject("memory")
system = Param.System(Parent.any, "system object")
cpu_id = Param.Int("CPU identifier")
@@ -47,7 +46,6 @@ class BaseCPU(SimObject):
self.icache_port = ic.cpu_side
self.dcache_port = dc.cpu_side
self._mem_ports = ['icache.mem_side', 'dcache.mem_side']
-# self.mem = dc
def addTwoLevelCacheHierarchy(self, ic, dc, l2c):
self.addPrivateSplitL1Caches(ic, dc)