diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2007-05-10 00:08:22 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-05-10 00:08:22 -0400 |
| commit | 4a37c48e8e74405c39899e4914656930869f8bd4 (patch) | |
| tree | cf05094448323e7efd7ad90f3340e14d66e96b54 /src/python/m5/objects | |
| parent | 69ea50c1635bc3dc455eeb29a6f7b0ff04e4ad0b (diff) | |
| download | gem5-4a37c48e8e74405c39899e4914656930869f8bd4.tar.xz | |
add/update parameters for bus bridge
--HG--
extra : convert_revision : 063f757fbfa2c613328ffa70e556f8926623fa91
Diffstat (limited to 'src/python/m5/objects')
| -rw-r--r-- | src/python/m5/objects/Bridge.py | 7 | ||||
| -rw-r--r-- | src/python/m5/objects/Device.py | 6 |
2 files changed, 11 insertions, 2 deletions
diff --git a/src/python/m5/objects/Bridge.py b/src/python/m5/objects/Bridge.py index e123c2891..33b24ad3c 100644 --- a/src/python/m5/objects/Bridge.py +++ b/src/python/m5/objects/Bridge.py @@ -5,9 +5,12 @@ class Bridge(MemObject): type = 'Bridge' side_a = Port('Side A port') side_b = Port('Side B port') - queue_size_a = Param.Int(16, "The number of requests to buffer") - queue_size_b = Param.Int(16, "The number of requests to buffer") + req_size_a = Param.Int(16, "The number of requests to buffer") + req_size_b = Param.Int(16, "The number of requests to buffer") + resp_size_a = Param.Int(16, "The number of requests to buffer") + resp_size_b = Param.Int(16, "The number of requests to buffer") delay = Param.Latency('0ns', "The latency of this bridge") + nack_delay = Param.Latency('0ns', "The latency of this bridge") write_ack = Param.Bool(False, "Should this bridge ack writes") fix_partial_write_a = Param.Bool(False, "Should this bridge fixup partial block writes") fix_partial_write_b = Param.Bool(False, "Should this bridge fixup partial block writes") diff --git a/src/python/m5/objects/Device.py b/src/python/m5/objects/Device.py index f4b873a60..90fbfb552 100644 --- a/src/python/m5/objects/Device.py +++ b/src/python/m5/objects/Device.py @@ -19,6 +19,12 @@ class DmaDevice(PioDevice): type = 'DmaDevice' abstract = True dma = Port(Self.pio.peerObj.port, "DMA port") + min_backoff_delay = Param.Latency('4ns', + "min time between a nack packet being received and the next request made by the device") + max_backoff_delay = Param.Latency('10us', + "max time between a nack packet being received and the next request made by the device") + + class IsaFake(BasicPioDevice): type = 'IsaFake' |