diff options
author | Gabe Black <gblack@eecs.umich.edu> | 2006-10-09 18:19:35 -0400 |
---|---|---|
committer | Gabe Black <gblack@eecs.umich.edu> | 2006-10-09 18:19:35 -0400 |
commit | a23c6a719323f2ac74cadd3b04c84f3dc679c26e (patch) | |
tree | 73e081aa0b1868834e8cf4ec98ce5254c6b5192e /src/python/m5/objects | |
parent | 187dcb18bfd87db63ad914d2ba04f0bd2dc0637d (diff) | |
parent | 727dea78c4b603a63d6c8bee10d317cb2905ffd4 (diff) | |
download | gem5-a23c6a719323f2ac74cadd3b04c84f3dc679c26e.tar.xz |
Merge zizzer.eecs.umich.edu:/bk/newmem
into zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus
--HG--
extra : convert_revision : 8267487b935eaf11665841ace3a5c664751b53b0
Diffstat (limited to 'src/python/m5/objects')
-rw-r--r-- | src/python/m5/objects/MemTest.py | 10 | ||||
-rw-r--r-- | src/python/m5/objects/PhysicalMemory.py | 1 |
2 files changed, 7 insertions, 4 deletions
diff --git a/src/python/m5/objects/MemTest.py b/src/python/m5/objects/MemTest.py index 97600768f..18aff03f4 100644 --- a/src/python/m5/objects/MemTest.py +++ b/src/python/m5/objects/MemTest.py @@ -1,13 +1,12 @@ from m5.SimObject import SimObject from m5.params import * +from m5.proxy import * +from m5 import build_env + class MemTest(SimObject): type = 'MemTest' - cache = Param.BaseCache("L1 cache") - check_mem = Param.FunctionalMemory("check memory") - main_mem = Param.FunctionalMemory("hierarchical memory") max_loads = Param.Counter("number of loads to execute") memory_size = Param.Int(65536, "memory size") - percent_copies = Param.Percent(0, "target copy percentage") percent_dest_unaligned = Param.Percent(50, "percent of copy dest address that are unaligned") percent_reads = Param.Percent(65, "target read percentage") @@ -18,3 +17,6 @@ class MemTest(SimObject): progress_interval = Param.Counter(1000000, "progress report interval (in accesses)") trace_addr = Param.Addr(0, "address to trace") + + test = Port("Port to the memory system to test") + functional = Port("Port to the functional memory used for verification") diff --git a/src/python/m5/objects/PhysicalMemory.py b/src/python/m5/objects/PhysicalMemory.py index dd3ffd651..4e097543d 100644 --- a/src/python/m5/objects/PhysicalMemory.py +++ b/src/python/m5/objects/PhysicalMemory.py @@ -5,6 +5,7 @@ from MemObject import * class PhysicalMemory(MemObject): type = 'PhysicalMemory' port = Port("the access port") + functional = Port("Functional Access Port") range = Param.AddrRange(AddrRange('128MB'), "Device Address") file = Param.String('', "memory mapped file") latency = Param.Latency(Parent.clock, "latency of an access") |