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authorGabe Black <gblack@eecs.umich.edu>2006-11-16 12:34:10 -0500
committerGabe Black <gblack@eecs.umich.edu>2006-11-16 12:34:10 -0500
commitcd5b33b9ff4016427fa93655f4bbd9030c4f5612 (patch)
treeb449360088378c982f59568c0a2da0c45cb08c59 /src/python/m5/objects
parent079dd454175ab7fdb3cc429f3cf199bd243c3776 (diff)
downloadgem5-cd5b33b9ff4016427fa93655f4bbd9030c4f5612.tar.xz
Fixes for SPARC_FS
configs/common/FSConfig.py: Make a SPARC system create an IO bus. src/python/m5/objects/T1000.py: Create a T1000 platform src/arch/sparc/miscregfile.cc: Initialize the strand status register to the value legion provides. src/cpu/exetrace.cc: Truncate an ExtMachInst to a MachInst before comparing with Legion. --HG-- extra : convert_revision : e4189b572a5297e8362f5bd26d87b74736c8e5f1
Diffstat (limited to 'src/python/m5/objects')
-rw-r--r--src/python/m5/objects/T1000.py53
1 files changed, 4 insertions, 49 deletions
diff --git a/src/python/m5/objects/T1000.py b/src/python/m5/objects/T1000.py
index e198d8566..bb0d37bf8 100644
--- a/src/python/m5/objects/T1000.py
+++ b/src/python/m5/objects/T1000.py
@@ -1,11 +1,9 @@
from m5.params import *
from m5.proxy import *
from Device import BasicPioDevice
-from Platform import Platform
-from AlphaConsole import AlphaConsole
from Uart import Uart8250
-from Pci import PciConfigAll
-from BadDevice import BadDevice
+from Platform import Platform
+from SimConsole import SimConsole, ConsoleListener
class IsaFake(BasicPioDevice):
type = 'IsaFake'
@@ -22,55 +20,12 @@ class T1000(Platform):
fake_iob = IsaFake(pio_addr=0x8000000000, pio_size=0x7F00000000)
- fake_uart1 = IsaFake(pio_addr=0x801fc0002f8)
- fake_uart2 = IsaFake(pio_addr=0x801fc0003e8)
- fake_uart3 = IsaFake(pio_addr=0x801fc0002e8)
- fake_uart4 = IsaFake(pio_addr=0x801fc0003f0)
-
- fake_ppc = IsaFake(pio_addr=0x801fc0003bc)
-
- fake_OROM = IsaFake(pio_addr=0x800000a0000, pio_size=0x60000)
-
- fake_pnp_addr = IsaFake(pio_addr=0x801fc000279)
- fake_pnp_write = IsaFake(pio_addr=0x801fc000a79)
- fake_pnp_read0 = IsaFake(pio_addr=0x801fc000203)
- fake_pnp_read1 = IsaFake(pio_addr=0x801fc000243)
- fake_pnp_read2 = IsaFake(pio_addr=0x801fc000283)
- fake_pnp_read3 = IsaFake(pio_addr=0x801fc0002c3)
- fake_pnp_read4 = IsaFake(pio_addr=0x801fc000303)
- fake_pnp_read5 = IsaFake(pio_addr=0x801fc000343)
- fake_pnp_read6 = IsaFake(pio_addr=0x801fc000383)
- fake_pnp_read7 = IsaFake(pio_addr=0x801fc0003c3)
-
- fake_ata0 = IsaFake(pio_addr=0x801fc0001f0)
- fake_ata1 = IsaFake(pio_addr=0x801fc000170)
-
- fb = BadDevice(pio_addr=0x801fc0003d0, devicename='FrameBuffer')
- uart = Uart8250(pio_addr=0x801fc0003f8)
+ uart = Uart8250(pio_addr=0xfff0c2c000)
+ console = SimConsole(listener = ConsoleListener())
# Attach I/O devices to specified bus object. Can't do this
# earlier, since the bus object itself is typically defined at the
# System level.
def attachIO(self, bus):
self.fake_iob.pio = bus.port
- self.fake_uart1.pio = bus.port
- self.fake_uart2.pio = bus.port
- self.fake_uart3.pio = bus.port
- self.fake_uart4.pio = bus.port
- self.fake_ppc.pio = bus.port
- self.fake_OROM.pio = bus.port
- self.fake_pnp_addr.pio = bus.port
- self.fake_pnp_write.pio = bus.port
- self.fake_pnp_read0.pio = bus.port
- self.fake_pnp_read1.pio = bus.port
- self.fake_pnp_read2.pio = bus.port
- self.fake_pnp_read3.pio = bus.port
- self.fake_pnp_read4.pio = bus.port
- self.fake_pnp_read5.pio = bus.port
- self.fake_pnp_read6.pio = bus.port
- self.fake_pnp_read7.pio = bus.port
- self.fake_ata0.pio = bus.port
- self.fake_ata1.pio = bus.port
- self.fb.pio = bus.port
- self.io.pio = bus.port
self.uart.pio = bus.port