Merge m5.eecs.umich.edu:/bk/newmem

into  ewok.(none):/home/gblack/m5/newmem

src/arch/sparc/regfile.hh:
    Hand Merge

--HG--
extra : convert_revision : c47202689202069892524a7d71962082469996ee

30 files changed, 245 insertions, 41 deletions

diff --git a/src/python/m5/objects/AlphaConsole.py b/src/python/m5/objects/AlphaConsole.py
index 68e6089ab..329b8c5bd 100644
--- a/src/python/m5/objects/AlphaConsole.py
+++ b/src/python/m5/objects/AlphaConsole.py
@@ -1,4 +1,4 @@
-from m5 import *
+from m5.config import *
 from Device import BasicPioDevice
 
 class AlphaConsole(BasicPioDevice):
diff --git a/src/python/m5/objects/AlphaFullCPU.py b/src/python/m5/objects/AlphaFullCPU.py
index 48989d057..2988305d3 100644
--- a/src/python/m5/objects/AlphaFullCPU.py
+++ b/src/python/m5/objects/AlphaFullCPU.py
@@ -1,13 +1,15 @@
-from m5 import *
+from m5 import build_env
+from m5.config import *
 from BaseCPU import BaseCPU
 
 class DerivAlphaFullCPU(BaseCPU):
     type = 'DerivAlphaFullCPU'
-
+    activity = Param.Unsigned("Initial count")
     numThreads = Param.Unsigned("number of HW thread contexts")
 
-    if not build_env['FULL_SYSTEM']:
-        mem = Param.FunctionalMemory(NULL, "memory")
+    checker = Param.BaseCPU(NULL, "checker")
+
+    cachePorts = Param.Unsigned("Cache Ports")
 
     decodeToFetchDelay = Param.Unsigned("Decode to fetch delay")
     renameToFetchDelay = Param.Unsigned("Rename to fetch delay")
@@ -41,22 +43,26 @@ class DerivAlphaFullCPU(BaseCPU):
     executeFloatWidth = Param.Unsigned("Floating point execute width")
     executeBranchWidth = Param.Unsigned("Branch execute width")
     executeMemoryWidth = Param.Unsigned("Memory execute width")
+    fuPool = Param.FUPool(NULL, "Functional Unit pool")
 
     iewToCommitDelay = Param.Unsigned("Issue/Execute/Writeback to commit "
                "delay")
     renameToROBDelay = Param.Unsigned("Rename to reorder buffer delay")
     commitWidth = Param.Unsigned("Commit width")
     squashWidth = Param.Unsigned("Squash width")
+    trapLatency = Param.Tick("Trap latency")
+    fetchTrapLatency = Param.Tick("Fetch trap latency")
 
-    local_predictor_size = Param.Unsigned("Size of local predictor")
-    local_ctr_bits = Param.Unsigned("Bits per counter")
-    local_history_table_size = Param.Unsigned("Size of local history table")
-    local_history_bits = Param.Unsigned("Bits for the local history")
-    global_predictor_size = Param.Unsigned("Size of global predictor")
-    global_ctr_bits = Param.Unsigned("Bits per counter")
-    global_history_bits = Param.Unsigned("Bits of history")
-    choice_predictor_size = Param.Unsigned("Size of choice predictor")
-    choice_ctr_bits = Param.Unsigned("Bits of choice counters")
+    predType = Param.String("Branch predictor type ('local', 'tournament')")
+    localPredictorSize = Param.Unsigned("Size of local predictor")
+    localCtrBits = Param.Unsigned("Bits per counter")
+    localHistoryTableSize = Param.Unsigned("Size of local history table")
+    localHistoryBits = Param.Unsigned("Bits for the local history")
+    globalPredictorSize = Param.Unsigned("Size of global predictor")
+    globalCtrBits = Param.Unsigned("Bits per counter")
+    globalHistoryBits = Param.Unsigned("Bits of history")
+    choicePredictorSize = Param.Unsigned("Size of choice predictor")
+    choiceCtrBits = Param.Unsigned("Bits of choice counters")
 
     BTBEntries = Param.Unsigned("Number of BTB entries")
     BTBTagSize = Param.Unsigned("Size of the BTB tags, in bits")
@@ -68,6 +74,8 @@ class DerivAlphaFullCPU(BaseCPU):
     LFSTSize = Param.Unsigned("Last fetched store table size")
     SSITSize = Param.Unsigned("Store set ID table size")
 
+    numRobs = Param.Unsigned("Number of Reorder Buffers");
+
     numPhysIntRegs = Param.Unsigned("Number of physical integer registers")
     numPhysFloatRegs = Param.Unsigned("Number of physical floating point "
                "registers")
@@ -78,3 +86,13 @@ class DerivAlphaFullCPU(BaseCPU):
 
     function_trace = Param.Bool(False, "Enable function trace")
     function_trace_start = Param.Tick(0, "Cycle to start function trace")
+
+    smtNumFetchingThreads = Param.Unsigned("SMT Number of Fetching Threads")
+    smtFetchPolicy = Param.String("SMT Fetch policy")
+    smtLSQPolicy    = Param.String("SMT LSQ Sharing Policy")
+    smtLSQThreshold = Param.String("SMT LSQ Threshold Sharing Parameter")
+    smtIQPolicy    = Param.String("SMT IQ Sharing Policy")
+    smtIQThreshold = Param.String("SMT IQ Threshold Sharing Parameter")
+    smtROBPolicy   = Param.String("SMT ROB Sharing Policy")
+    smtROBThreshold = Param.String("SMT ROB Threshold Sharing Parameter")
+    smtCommitPolicy = Param.String("SMT Commit Policy")
diff --git a/src/python/m5/objects/AlphaTLB.py b/src/python/m5/objects/AlphaTLB.py
index 5edf8e13d..11c1792ee 100644
--- a/src/python/m5/objects/AlphaTLB.py
+++ b/src/python/m5/objects/AlphaTLB.py
@@ -1,4 +1,4 @@
-from m5 import *
+from m5.config import *
 class AlphaTLB(SimObject):
     type = 'AlphaTLB'
     abstract = True
diff --git a/src/python/m5/objects/BadDevice.py b/src/python/m5/objects/BadDevice.py
index 9cb9a8f03..186b733fa 100644
--- a/src/python/m5/objects/BadDevice.py
+++ b/src/python/m5/objects/BadDevice.py
@@ -1,4 +1,4 @@
-from m5 import *
+from m5.config import *
 from Device import BasicPioDevice
 
 class BadDevice(BasicPioDevice):
diff --git a/src/python/m5/objects/BaseCPU.py b/src/python/m5/objects/BaseCPU.py
index 49cb2a8f3..2e78578df 100644
--- a/src/python/m5/objects/BaseCPU.py
+++ b/src/python/m5/objects/BaseCPU.py
@@ -1,4 +1,6 @@
-from m5 import *
+from m5 import build_env
+from m5.config import *
+
 class BaseCPU(SimObject):
     type = 'BaseCPU'
     abstract = True
diff --git a/src/python/m5/objects/BaseCache.py b/src/python/m5/objects/BaseCache.py
index 79d21572a..33f44759b 100644
--- a/src/python/m5/objects/BaseCache.py
+++ b/src/python/m5/objects/BaseCache.py
@@ -1,4 +1,4 @@
-from m5 import *
+from m5.config import *
 from BaseMem import BaseMem
 
 class Prefetch(Enum): vals = ['none', 'tagged', 'stride', 'ghb']
diff --git a/src/python/m5/objects/Bridge.py b/src/python/m5/objects/Bridge.py
index ada715ce9..880535755 100644
--- a/src/python/m5/objects/Bridge.py
+++ b/src/python/m5/objects/Bridge.py
@@ -1,4 +1,4 @@
-from m5 import *
+from m5.config import *
 from MemObject import MemObject
 
 class Bridge(MemObject):
diff --git a/src/python/m5/objects/Bus.py b/src/python/m5/objects/Bus.py
index 8c5397281..c37dab438 100644
--- a/src/python/m5/objects/Bus.py
+++ b/src/python/m5/objects/Bus.py
@@ -1,4 +1,4 @@
-from m5 import *
+from m5.config import *
 from MemObject import MemObject
 
 class Bus(MemObject):
diff --git a/src/python/m5/objects/CoherenceProtocol.py b/src/python/m5/objects/CoherenceProtocol.py
index 7013000d6..64b6cbacf 100644
--- a/src/python/m5/objects/CoherenceProtocol.py
+++ b/src/python/m5/objects/CoherenceProtocol.py
@@ -1,4 +1,4 @@
-from m5 import *
+from m5.config import *
 class Coherence(Enum): vals = ['uni', 'msi', 'mesi', 'mosi', 'moesi']
 
 class CoherenceProtocol(SimObject):
diff --git a/src/python/m5/objects/Device.py b/src/python/m5/objects/Device.py
index 2a71bbc65..7798f5f04 100644
--- a/src/python/m5/objects/Device.py
+++ b/src/python/m5/objects/Device.py
@@ -1,4 +1,4 @@
-from m5 import *
+from m5.config import *
 from MemObject import MemObject
 
 class PioDevice(MemObject):
diff --git a/src/python/m5/objects/DiskImage.py b/src/python/m5/objects/DiskImage.py
index 0d55e9329..70d8b2e45 100644
--- a/src/python/m5/objects/DiskImage.py
+++ b/src/python/m5/objects/DiskImage.py
@@ -1,4 +1,4 @@
-from m5 import *
+from m5.config import *
 class DiskImage(SimObject):
     type = 'DiskImage'
     abstract = True
diff --git a/src/python/m5/objects/Ethernet.py b/src/python/m5/objects/Ethernet.py
index 4286c71c8..418670592 100644
--- a/src/python/m5/objects/Ethernet.py
+++ b/src/python/m5/objects/Ethernet.py
@@ -1,4 +1,5 @@
-from m5 import *
+from m5 import build_env
+from m5.config import *
 from Device import DmaDevice
 from Pci import PciDevice
 
diff --git a/src/python/m5/objects/FUPool.py b/src/python/m5/objects/FUPool.py
new file mode 100644
index 000000000..cbf1089cf
--- /dev/null
+++ b/src/python/m5/objects/FUPool.py
@@ -0,0 +1,5 @@
+from m5.config import *
+
+class FUPool(SimObject):
+    type = 'FUPool'
+    FUList = VectorParam.FUDesc("list of FU's for this pool")
diff --git a/src/python/m5/objects/Ide.py b/src/python/m5/objects/Ide.py
index 2403e6d36..9ee578177 100644
--- a/src/python/m5/objects/Ide.py
+++ b/src/python/m5/objects/Ide.py
@@ -1,4 +1,4 @@
-from m5 import *
+from m5.config import *
 from Pci import PciDevice
 
 class IdeID(Enum): vals = ['master', 'slave']
diff --git a/src/python/m5/objects/IntrControl.py b/src/python/m5/objects/IntrControl.py
index 66c82c182..514c3fc62 100644
--- a/src/python/m5/objects/IntrControl.py
+++ b/src/python/m5/objects/IntrControl.py
@@ -1,4 +1,4 @@
-from m5 import *
+from m5.config import *
 class IntrControl(SimObject):
     type = 'IntrControl'
     cpu = Param.BaseCPU(Parent.any, "the cpu")
diff --git a/src/python/m5/objects/MemObject.py b/src/python/m5/objects/MemObject.py
index 4d68243e6..d957dae17 100644
--- a/src/python/m5/objects/MemObject.py
+++ b/src/python/m5/objects/MemObject.py
@@ -1,4 +1,4 @@
-from m5 import *
+from m5.config import *
 
 class MemObject(SimObject):
     type = 'MemObject'
diff --git a/src/python/m5/objects/MemTest.py b/src/python/m5/objects/MemTest.py
index 34299faf0..9916d7cb4 100644
--- a/src/python/m5/objects/MemTest.py
+++ b/src/python/m5/objects/MemTest.py
@@ -1,4 +1,4 @@
-from m5 import *
+from m5.config import *
 class MemTest(SimObject):
     type = 'MemTest'
     cache = Param.BaseCache("L1 cache")
diff --git a/src/python/m5/objects/OzoneCPU.py b/src/python/m5/objects/OzoneCPU.py
new file mode 100644
index 000000000..f2d9aea84
--- /dev/null
+++ b/src/python/m5/objects/OzoneCPU.py
@@ -0,0 +1,91 @@
+from m5 import build_env
+from m5.config import *
+from BaseCPU import BaseCPU
+
+class DerivOzoneCPU(BaseCPU):
+    type = 'DerivOzoneCPU'
+
+    numThreads = Param.Unsigned("number of HW thread contexts")
+
+    if not build_env['FULL_SYSTEM']:
+        mem = Param.FunctionalMemory(NULL, "memory")
+
+    checker = Param.BaseCPU("Checker CPU")
+
+    width = Param.Unsigned("Width")
+    frontEndWidth = Param.Unsigned("Front end width")
+    backEndWidth = Param.Unsigned("Back end width")
+    backEndSquashLatency = Param.Unsigned("Back end squash latency")
+    backEndLatency = Param.Unsigned("Back end latency")
+    maxInstBufferSize = Param.Unsigned("Maximum instruction buffer size")
+    maxOutstandingMemOps = Param.Unsigned("Maximum number of outstanding memory operations")
+    decodeToFetchDelay = Param.Unsigned("Decode to fetch delay")
+    renameToFetchDelay = Param.Unsigned("Rename to fetch delay")
+    iewToFetchDelay = Param.Unsigned("Issue/Execute/Writeback to fetch "
+               "delay")
+    commitToFetchDelay = Param.Unsigned("Commit to fetch delay")
+    fetchWidth = Param.Unsigned("Fetch width")
+
+    renameToDecodeDelay = Param.Unsigned("Rename to decode delay")
+    iewToDecodeDelay = Param.Unsigned("Issue/Execute/Writeback to decode "
+               "delay")
+    commitToDecodeDelay = Param.Unsigned("Commit to decode delay")
+    fetchToDecodeDelay = Param.Unsigned("Fetch to decode delay")
+    decodeWidth = Param.Unsigned("Decode width")
+
+    iewToRenameDelay = Param.Unsigned("Issue/Execute/Writeback to rename "
+               "delay")
+    commitToRenameDelay = Param.Unsigned("Commit to rename delay")
+    decodeToRenameDelay = Param.Unsigned("Decode to rename delay")
+    renameWidth = Param.Unsigned("Rename width")
+
+    commitToIEWDelay = Param.Unsigned("Commit to "
+               "Issue/Execute/Writeback delay")
+    renameToIEWDelay = Param.Unsigned("Rename to "
+               "Issue/Execute/Writeback delay")
+    issueToExecuteDelay = Param.Unsigned("Issue to execute delay (internal "
+              "to the IEW stage)")
+    issueWidth = Param.Unsigned("Issue width")
+    executeWidth = Param.Unsigned("Execute width")
+    executeIntWidth = Param.Unsigned("Integer execute width")
+    executeFloatWidth = Param.Unsigned("Floating point execute width")
+    executeBranchWidth = Param.Unsigned("Branch execute width")
+    executeMemoryWidth = Param.Unsigned("Memory execute width")
+
+    iewToCommitDelay = Param.Unsigned("Issue/Execute/Writeback to commit "
+               "delay")
+    renameToROBDelay = Param.Unsigned("Rename to reorder buffer delay")
+    commitWidth = Param.Unsigned("Commit width")
+    squashWidth = Param.Unsigned("Squash width")
+
+    predType = Param.String("Type of branch predictor ('local', 'tournament')")
+    localPredictorSize = Param.Unsigned("Size of local predictor")
+    localCtrBits = Param.Unsigned("Bits per counter")
+    localHistoryTableSize = Param.Unsigned("Size of local history table")
+    localHistoryBits = Param.Unsigned("Bits for the local history")
+    globalPredictorSize = Param.Unsigned("Size of global predictor")
+    globalCtrBits = Param.Unsigned("Bits per counter")
+    globalHistoryBits = Param.Unsigned("Bits of history")
+    choicePredictorSize = Param.Unsigned("Size of choice predictor")
+    choiceCtrBits = Param.Unsigned("Bits of choice counters")
+
+    BTBEntries = Param.Unsigned("Number of BTB entries")
+    BTBTagSize = Param.Unsigned("Size of the BTB tags, in bits")
+
+    RASSize = Param.Unsigned("RAS size")
+
+    LQEntries = Param.Unsigned("Number of load queue entries")
+    SQEntries = Param.Unsigned("Number of store queue entries")
+    LFSTSize = Param.Unsigned("Last fetched store table size")
+    SSITSize = Param.Unsigned("Store set ID table size")
+
+    numPhysIntRegs = Param.Unsigned("Number of physical integer registers")
+    numPhysFloatRegs = Param.Unsigned("Number of physical floating point "
+               "registers")
+    numIQEntries = Param.Unsigned("Number of instruction queue entries")
+    numROBEntries = Param.Unsigned("Number of reorder buffer entries")
+
+    instShiftAmt = Param.Unsigned("Number of bits to shift instructions by")
+
+    function_trace = Param.Bool(False, "Enable function trace")
+    function_trace_start = Param.Tick(0, "Cycle to start function trace")
diff --git a/src/python/m5/objects/Pci.py b/src/python/m5/objects/Pci.py
index 85cefcd44..9e1e91b13 100644
--- a/src/python/m5/objects/Pci.py
+++ b/src/python/m5/objects/Pci.py
@@ -1,4 +1,4 @@
-from m5 import *
+from m5.config import *
 from Device import BasicPioDevice, DmaDevice
 
 class PciConfigData(SimObject):
diff --git a/src/python/m5/objects/PhysicalMemory.py b/src/python/m5/objects/PhysicalMemory.py
index c59910093..bed90d555 100644
--- a/src/python/m5/objects/PhysicalMemory.py
+++ b/src/python/m5/objects/PhysicalMemory.py
@@ -1,4 +1,4 @@
-from m5 import *
+from m5.config import *
 from MemObject import *
 
 class PhysicalMemory(MemObject):
diff --git a/src/python/m5/objects/Platform.py b/src/python/m5/objects/Platform.py
index 4da0ffab4..89fee9991 100644
--- a/src/python/m5/objects/Platform.py
+++ b/src/python/m5/objects/Platform.py
@@ -1,4 +1,4 @@
-from m5 import *
+from m5.config import *
 class Platform(SimObject):
     type = 'Platform'
     abstract = True
diff --git a/src/python/m5/objects/Process.py b/src/python/m5/objects/Process.py
index 60b00229e..0091d8654 100644
--- a/src/python/m5/objects/Process.py
+++ b/src/python/m5/objects/Process.py
@@ -1,4 +1,4 @@
-from m5 import *
+from m5.config import *
 class Process(SimObject):
     type = 'Process'
     abstract = True
diff --git a/src/python/m5/objects/Repl.py b/src/python/m5/objects/Repl.py
index afd256082..8e9f1094f 100644
--- a/src/python/m5/objects/Repl.py
+++ b/src/python/m5/objects/Repl.py
@@ -1,4 +1,4 @@
-from m5 import *
+from m5.config import *
 class Repl(SimObject):
     type = 'Repl'
     abstract = True
diff --git a/src/python/m5/objects/Root.py b/src/python/m5/objects/Root.py
index 205a93c76..373475a7a 100644
--- a/src/python/m5/objects/Root.py
+++ b/src/python/m5/objects/Root.py
@@ -1,4 +1,4 @@
-from m5 import *
+from m5.config import *
 from Serialize import Serialize
 from Statistics import Statistics
 from Trace import Trace
diff --git a/src/python/m5/objects/SimConsole.py b/src/python/m5/objects/SimConsole.py
index df3061908..9e1452c6d 100644
--- a/src/python/m5/objects/SimConsole.py
+++ b/src/python/m5/objects/SimConsole.py
@@ -1,4 +1,4 @@
-from m5 import *
+from m5.config import *
 class ConsoleListener(SimObject):
     type = 'ConsoleListener'
     port = Param.TcpPort(3456, "listen port")
diff --git a/src/python/m5/objects/SimpleDisk.py b/src/python/m5/objects/SimpleDisk.py
index e34155ace..44ef709af 100644
--- a/src/python/m5/objects/SimpleDisk.py
+++ b/src/python/m5/objects/SimpleDisk.py
@@ -1,4 +1,4 @@
-from m5 import *
+from m5.config import *
 class SimpleDisk(SimObject):
     type = 'SimpleDisk'
     disk = Param.DiskImage("Disk Image")
diff --git a/src/python/m5/objects/SimpleOzoneCPU.py b/src/python/m5/objects/SimpleOzoneCPU.py
new file mode 100644
index 000000000..5d968cab0
--- /dev/null
+++ b/src/python/m5/objects/SimpleOzoneCPU.py
@@ -0,0 +1,87 @@
+from m5 import build_env
+from m5.config import *
+from BaseCPU import BaseCPU
+
+class SimpleOzoneCPU(BaseCPU):
+    type = 'SimpleOzoneCPU'
+
+    numThreads = Param.Unsigned("number of HW thread contexts")
+
+    if not build_env['FULL_SYSTEM']:
+        mem = Param.FunctionalMemory(NULL, "memory")
+
+    width = Param.Unsigned("Width")
+    frontEndWidth = Param.Unsigned("Front end width")
+    backEndWidth = Param.Unsigned("Back end width")
+    backEndSquashLatency = Param.Unsigned("Back end squash latency")
+    backEndLatency = Param.Unsigned("Back end latency")
+    maxInstBufferSize = Param.Unsigned("Maximum instruction buffer size")
+    decodeToFetchDelay = Param.Unsigned("Decode to fetch delay")
+    renameToFetchDelay = Param.Unsigned("Rename to fetch delay")
+    iewToFetchDelay = Param.Unsigned("Issue/Execute/Writeback to fetch "
+               "delay")
+    commitToFetchDelay = Param.Unsigned("Commit to fetch delay")
+    fetchWidth = Param.Unsigned("Fetch width")
+
+    renameToDecodeDelay = Param.Unsigned("Rename to decode delay")
+    iewToDecodeDelay = Param.Unsigned("Issue/Execute/Writeback to decode "
+               "delay")
+    commitToDecodeDelay = Param.Unsigned("Commit to decode delay")
+    fetchToDecodeDelay = Param.Unsigned("Fetch to decode delay")
+    decodeWidth = Param.Unsigned("Decode width")
+
+    iewToRenameDelay = Param.Unsigned("Issue/Execute/Writeback to rename "
+               "delay")
+    commitToRenameDelay = Param.Unsigned("Commit to rename delay")
+    decodeToRenameDelay = Param.Unsigned("Decode to rename delay")
+    renameWidth = Param.Unsigned("Rename width")
+
+    commitToIEWDelay = Param.Unsigned("Commit to "
+               "Issue/Execute/Writeback delay")
+    renameToIEWDelay = Param.Unsigned("Rename to "
+               "Issue/Execute/Writeback delay")
+    issueToExecuteDelay = Param.Unsigned("Issue to execute delay (internal "
+              "to the IEW stage)")
+    issueWidth = Param.Unsigned("Issue width")
+    executeWidth = Param.Unsigned("Execute width")
+    executeIntWidth = Param.Unsigned("Integer execute width")
+    executeFloatWidth = Param.Unsigned("Floating point execute width")
+    executeBranchWidth = Param.Unsigned("Branch execute width")
+    executeMemoryWidth = Param.Unsigned("Memory execute width")
+
+    iewToCommitDelay = Param.Unsigned("Issue/Execute/Writeback to commit "
+               "delay")
+    renameToROBDelay = Param.Unsigned("Rename to reorder buffer delay")
+    commitWidth = Param.Unsigned("Commit width")
+    squashWidth = Param.Unsigned("Squash width")
+
+    localPredictorSize = Param.Unsigned("Size of local predictor")
+    localCtrBits = Param.Unsigned("Bits per counter")
+    localHistoryTableSize = Param.Unsigned("Size of local history table")
+    localHistoryBits = Param.Unsigned("Bits for the local history")
+    globalPredictorSize = Param.Unsigned("Size of global predictor")
+    globalCtrBits = Param.Unsigned("Bits per counter")
+    globalHistoryBits = Param.Unsigned("Bits of history")
+    choicePredictorSize = Param.Unsigned("Size of choice predictor")
+    choiceCtrBits = Param.Unsigned("Bits of choice counters")
+
+    BTBEntries = Param.Unsigned("Number of BTB entries")
+    BTBTagSize = Param.Unsigned("Size of the BTB tags, in bits")
+
+    RASSize = Param.Unsigned("RAS size")
+
+    LQEntries = Param.Unsigned("Number of load queue entries")
+    SQEntries = Param.Unsigned("Number of store queue entries")
+    LFSTSize = Param.Unsigned("Last fetched store table size")
+    SSITSize = Param.Unsigned("Store set ID table size")
+
+    numPhysIntRegs = Param.Unsigned("Number of physical integer registers")
+    numPhysFloatRegs = Param.Unsigned("Number of physical floating point "
+               "registers")
+    numIQEntries = Param.Unsigned("Number of instruction queue entries")
+    numROBEntries = Param.Unsigned("Number of reorder buffer entries")
+
+    instShiftAmt = Param.Unsigned("Number of bits to shift instructions by")
+
+    function_trace = Param.Bool(False, "Enable function trace")
+    function_trace_start = Param.Tick(0, "Cycle to start function trace")
diff --git a/src/python/m5/objects/System.py b/src/python/m5/objects/System.py
index 622b5a870..9a1e1d690 100644
--- a/src/python/m5/objects/System.py
+++ b/src/python/m5/objects/System.py
@@ -1,4 +1,5 @@
-from m5 import *
+from m5 import build_env
+from m5.config import *
 
 class System(SimObject):
     type = 'System'
@@ -7,8 +8,6 @@ class System(SimObject):
         boot_cpu_frequency = Param.Frequency(Self.cpu[0].clock.frequency,
                                              "boot processor frequency")
         init_param = Param.UInt64(0, "numerical value to pass into simulator")
-        bin = Param.Bool(False, "is this system binned")
-        binned_fns = VectorParam.String([], "functions broken down and binned")
         boot_osflags = Param.String("a", "boot flags to pass to the kernel")
         kernel = Param.String("file that contains the kernel code")
         readfile = Param.String("", "file to read startup script from")
diff --git a/src/python/m5/objects/Tsunami.py b/src/python/m5/objects/Tsunami.py
index 27ea0bce8..4613571d8 100644
--- a/src/python/m5/objects/Tsunami.py
+++ b/src/python/m5/objects/Tsunami.py
@@ -1,4 +1,4 @@
-from m5 import *
+from m5.config import *
 from Device import BasicPioDevice
 from Platform import Platform
 
diff --git a/src/python/m5/objects/Uart.py b/src/python/m5/objects/Uart.py
index 54754aeb9..8e1fd1a37 100644
--- a/src/python/m5/objects/Uart.py
+++ b/src/python/m5/objects/Uart.py
@@ -1,4 +1,5 @@
-from m5 import *
+from m5 import build_env
+from m5.config import *
 from Device import BasicPioDevice
 
 class Uart(BasicPioDevice):