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| author | Joel Hestness <hestness@cs.wisc.edu> | 2012-09-12 21:41:37 -0500 |
|---|---|---|
| committer | Joel Hestness <hestness@cs.wisc.edu> | 2012-09-12 21:41:37 -0500 |
| commit | 234fa4cf7ecd16350c1095830d26f94b2bfd3eb9 (patch) | |
| tree | b9e29dccf07623bd982d6042fa852c9b99f5390b /src/python/m5/simulate.py | |
| parent | 16dcb723c11afb91cc3428294bd3106425114949 (diff) | |
| download | gem5-234fa4cf7ecd16350c1095830d26f94b2bfd3eb9.tar.xz | |
Standard Switch: Drain the system before switching CPUs
When switching from an atomic CPU to any of the timing CPUs, a drain is
unnecessary since no events are scheduled in atomic mode. However, when
trying to switch CPUs starting with a timing CPU, there may be events
scheduled. This change ensures that all events are drained from the system
by calling m5.drain before switching CPUs.
Diffstat (limited to 'src/python/m5/simulate.py')
| -rw-r--r-- | src/python/m5/simulate.py | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/python/m5/simulate.py b/src/python/m5/simulate.py index 9cb647a6b..0f2a546c1 100644 --- a/src/python/m5/simulate.py +++ b/src/python/m5/simulate.py @@ -203,7 +203,6 @@ def changeToTiming(system): (type(system), objects.Root, objects.System) if system.getMemoryMode() != objects.params.timing: - doDrain(system) print "Changing memory mode to timing" for obj in system.descendants(): obj.changeTiming(objects.params.timing) |