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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-09-02 11:26:15 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-09-06 20:00:34 +0000 |
| commit | e7c75d2c114836203fb5c4d0a7d842c4f4ebaa0e (patch) | |
| tree | ef1931b5aaad562807fdd2cec75b80dbcf4331a0 /src/python/m5/util/dot_writer.py | |
| parent | 2a818db77ab5fe5cc7d716dd2aa88241550045a7 (diff) | |
| download | gem5-e7c75d2c114836203fb5c4d0a7d842c4f4ebaa0e.tar.xz | |
dev-arm: State update when setting MISCREG_ICC_IGRPENx register
This is because by enabling ainterrupt group at the cpu interface, we
need to check if a previously pending interrupt needs to be forwarded to
the PE.
We are doing the same when globally enabling irqs in the distributor
(GICD_CTLR).
Change-Id: I80aeb87b2a58a108de899006d5a2f12eadbe6c2e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20629
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/python/m5/util/dot_writer.py')
0 files changed, 0 insertions, 0 deletions