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authorSteve Reinhardt <stever@eecs.umich.edu>2006-09-04 17:14:07 -0700
committerSteve Reinhardt <stever@eecs.umich.edu>2006-09-04 17:14:07 -0700
commitc39aea440c884f0abb29ecc2293fd6df608bc00c (patch)
tree21642bd3db3f2e10989cb6c5cf34892b9efe6267 /src/python/m5
parent1233dbb9981ad27abeb22f9dcba20bd77abab041 (diff)
downloadgem5-c39aea440c884f0abb29ecc2293fd6df608bc00c.tar.xz
More Python hacking to deal with config.py split
and resulting recursive import trickiness. --HG-- extra : convert_revision : 1ea93861eb8d260c9f3920dda0b8106db3e03705
Diffstat (limited to 'src/python/m5')
-rw-r--r--src/python/m5/SimObject.py87
-rw-r--r--src/python/m5/__init__.py4
-rw-r--r--src/python/m5/objects/AlphaConsole.py3
-rw-r--r--src/python/m5/objects/AlphaTLB.py3
-rw-r--r--src/python/m5/objects/BadDevice.py2
-rw-r--r--src/python/m5/objects/BaseCPU.py4
-rw-r--r--src/python/m5/objects/BaseCache.py2
-rw-r--r--src/python/m5/objects/Bridge.py2
-rw-r--r--src/python/m5/objects/Bus.py2
-rw-r--r--src/python/m5/objects/CoherenceProtocol.py3
-rw-r--r--src/python/m5/objects/Device.py3
-rw-r--r--src/python/m5/objects/DiskImage.py3
-rw-r--r--src/python/m5/objects/Ethernet.py4
-rw-r--r--src/python/m5/objects/FUPool.py3
-rw-r--r--src/python/m5/objects/FuncUnit.py3
-rw-r--r--src/python/m5/objects/Ide.py3
-rw-r--r--src/python/m5/objects/IntrControl.py4
-rw-r--r--src/python/m5/objects/MemObject.py3
-rw-r--r--src/python/m5/objects/MemTest.py3
-rw-r--r--src/python/m5/objects/O3CPU.py3
-rw-r--r--src/python/m5/objects/OzoneCPU.py2
-rw-r--r--src/python/m5/objects/Pci.py4
-rw-r--r--src/python/m5/objects/PhysicalMemory.py3
-rw-r--r--src/python/m5/objects/Platform.py4
-rw-r--r--src/python/m5/objects/Process.py4
-rw-r--r--src/python/m5/objects/Repl.py3
-rw-r--r--src/python/m5/objects/Root.py3
-rw-r--r--src/python/m5/objects/SimConsole.py4
-rw-r--r--src/python/m5/objects/SimpleDisk.py4
-rw-r--r--src/python/m5/objects/SimpleOzoneCPU.py2
-rw-r--r--src/python/m5/objects/System.py4
-rw-r--r--src/python/m5/objects/Tsunami.py3
-rw-r--r--src/python/m5/objects/Uart.py3
-rw-r--r--src/python/m5/params.py66
34 files changed, 153 insertions, 100 deletions
diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py
index 33fa51665..b8b931d81 100644
--- a/src/python/m5/SimObject.py
+++ b/src/python/m5/SimObject.py
@@ -29,11 +29,40 @@
import sys, types
-import m5
-from m5 import panic, cc_main
-from convert import *
+from util import *
from multidict import multidict
+# These utility functions have to come first because they're
+# referenced in params.py... otherwise they won't be defined when we
+# import params below, and the recursive import of this file from
+# params.py will not find these names.
+def isSimObject(value):
+ return isinstance(value, SimObject)
+
+def isSimObjectClass(value):
+ return issubclass(value, SimObject)
+
+def isSimObjectSequence(value):
+ if not isinstance(value, (list, tuple)) or len(value) == 0:
+ return False
+
+ for val in value:
+ if not isNullPointer(val) and not isSimObject(val):
+ return False
+
+ return True
+
+def isSimObjectOrSequence(value):
+ return isSimObject(value) or isSimObjectSequence(value)
+
+# Have to import params up top since Param is referenced on initial
+# load (when SimObject class references Param to create a class
+# variable, the 'name' param)...
+from params import *
+# There are a few things we need that aren't in params.__all__ since
+# normal users don't need them
+from params import ParamDesc, isNullPointer, SimObjVector
+
noDot = False
try:
import pydot
@@ -564,7 +593,7 @@ class SimObject(object):
for param in param_names:
value = self._values.get(param, None)
if value != None:
- if isproxy(value):
+ if proxy.isproxy(value):
try:
value = value.unproxy(self)
except:
@@ -679,52 +708,6 @@ class SimObject(object):
class ParamContext(SimObject):
pass
-# Special class for NULL pointers. Note the special check in
-# make_param_value() above that lets these be assigned where a
-# SimObject is required.
-# only one copy of a particular node
-class NullSimObject(object):
- __metaclass__ = Singleton
-
- def __call__(cls):
- return cls
-
- def _instantiate(self, parent = None, path = ''):
- pass
-
- def ini_str(self):
- return 'Null'
-
- def unproxy(self, base):
- return self
-
- def set_path(self, parent, name):
- pass
- def __str__(self):
- return 'Null'
-
-# The only instance you'll ever need...
-Null = NULL = NullSimObject()
-
-def isSimObject(value):
- return isinstance(value, SimObject)
-
-def isNullPointer(value):
- return isinstance(value, NullSimObject)
-
-def isSimObjectSequence(value):
- if not isinstance(value, (list, tuple)) or len(value) == 0:
- return False
-
- for val in value:
- if not isNullPointer(val) and not isSimObject(val):
- return False
-
- return True
-
-def isSimObjectOrSequence(value):
- return isSimObject(value) or isSimObjectSequence(value)
-
# Function to provide to C++ so it can look up instances based on paths
def resolveSimObject(name):
obj = instanceDict[name]
@@ -735,3 +718,7 @@ def resolveSimObject(name):
# short to avoid polluting other namespaces.
__all__ = ['SimObject', 'ParamContext']
+
+# see comment on imports at end of __init__.py.
+import proxy
+import cc_main
diff --git a/src/python/m5/__init__.py b/src/python/m5/__init__.py
index bd2efac09..c37abbac9 100644
--- a/src/python/m5/__init__.py
+++ b/src/python/m5/__init__.py
@@ -71,8 +71,6 @@ build_env.update(defines.m5_build_env)
env = smartdict.SmartDict()
env.update(os.environ)
-from main import options, arguments, main
-
# The final hook to generate .ini files. Called from the user script
# once the config is built.
def instantiate(root):
@@ -206,5 +204,7 @@ def switchCpus(cpuList):
# you can get the wrong result if foo is only partially imported
# at the point you do that (i.e., because foo is in the middle of
# importing *you*).
+from main import options
import objects
import params
+from SimObject import resolveSimObject
diff --git a/src/python/m5/objects/AlphaConsole.py b/src/python/m5/objects/AlphaConsole.py
index 329b8c5bd..1c71493b1 100644
--- a/src/python/m5/objects/AlphaConsole.py
+++ b/src/python/m5/objects/AlphaConsole.py
@@ -1,4 +1,5 @@
-from m5.config import *
+from m5.params import *
+from m5.proxy import *
from Device import BasicPioDevice
class AlphaConsole(BasicPioDevice):
diff --git a/src/python/m5/objects/AlphaTLB.py b/src/python/m5/objects/AlphaTLB.py
index 11c1792ee..af7c04a84 100644
--- a/src/python/m5/objects/AlphaTLB.py
+++ b/src/python/m5/objects/AlphaTLB.py
@@ -1,4 +1,5 @@
-from m5.config import *
+from m5.SimObject import SimObject
+from m5.params import *
class AlphaTLB(SimObject):
type = 'AlphaTLB'
abstract = True
diff --git a/src/python/m5/objects/BadDevice.py b/src/python/m5/objects/BadDevice.py
index 186b733fa..919623887 100644
--- a/src/python/m5/objects/BadDevice.py
+++ b/src/python/m5/objects/BadDevice.py
@@ -1,4 +1,4 @@
-from m5.config import *
+from m5.params import *
from Device import BasicPioDevice
class BadDevice(BasicPioDevice):
diff --git a/src/python/m5/objects/BaseCPU.py b/src/python/m5/objects/BaseCPU.py
index 41e90b12b..3dd0bda01 100644
--- a/src/python/m5/objects/BaseCPU.py
+++ b/src/python/m5/objects/BaseCPU.py
@@ -1,5 +1,7 @@
+from m5.SimObject import SimObject
+from m5.params import *
+from m5.proxy import *
from m5 import build_env
-from m5.config import *
from AlphaTLB import AlphaDTB, AlphaITB
from Bus import Bus
diff --git a/src/python/m5/objects/BaseCache.py b/src/python/m5/objects/BaseCache.py
index 497b2b038..db58a177f 100644
--- a/src/python/m5/objects/BaseCache.py
+++ b/src/python/m5/objects/BaseCache.py
@@ -1,4 +1,4 @@
-from m5.config import *
+from m5.params import *
from MemObject import MemObject
class Prefetch(Enum): vals = ['none', 'tagged', 'stride', 'ghb']
diff --git a/src/python/m5/objects/Bridge.py b/src/python/m5/objects/Bridge.py
index c9e673afb..ee8e76bff 100644
--- a/src/python/m5/objects/Bridge.py
+++ b/src/python/m5/objects/Bridge.py
@@ -1,4 +1,4 @@
-from m5.config import *
+from m5.params import *
from MemObject import MemObject
class Bridge(MemObject):
diff --git a/src/python/m5/objects/Bus.py b/src/python/m5/objects/Bus.py
index e0278e6c3..f6828a0d5 100644
--- a/src/python/m5/objects/Bus.py
+++ b/src/python/m5/objects/Bus.py
@@ -1,4 +1,4 @@
-from m5.config import *
+from m5.params import *
from MemObject import MemObject
class Bus(MemObject):
diff --git a/src/python/m5/objects/CoherenceProtocol.py b/src/python/m5/objects/CoherenceProtocol.py
index 64b6cbacf..82adb6862 100644
--- a/src/python/m5/objects/CoherenceProtocol.py
+++ b/src/python/m5/objects/CoherenceProtocol.py
@@ -1,4 +1,5 @@
-from m5.config import *
+from m5.SimObject import SimObject
+from m5.params import *
class Coherence(Enum): vals = ['uni', 'msi', 'mesi', 'mosi', 'moesi']
class CoherenceProtocol(SimObject):
diff --git a/src/python/m5/objects/Device.py b/src/python/m5/objects/Device.py
index f72c8e73f..3e9094e25 100644
--- a/src/python/m5/objects/Device.py
+++ b/src/python/m5/objects/Device.py
@@ -1,4 +1,5 @@
-from m5.config import *
+from m5.params import *
+from m5.proxy import *
from MemObject import MemObject
class PioDevice(MemObject):
diff --git a/src/python/m5/objects/DiskImage.py b/src/python/m5/objects/DiskImage.py
index a98b35a4f..d0ada7ee1 100644
--- a/src/python/m5/objects/DiskImage.py
+++ b/src/python/m5/objects/DiskImage.py
@@ -1,4 +1,5 @@
-from m5.config import *
+from m5.SimObject import SimObject
+from m5.params import *
class DiskImage(SimObject):
type = 'DiskImage'
abstract = True
diff --git a/src/python/m5/objects/Ethernet.py b/src/python/m5/objects/Ethernet.py
index fb641bf80..609a3dd6f 100644
--- a/src/python/m5/objects/Ethernet.py
+++ b/src/python/m5/objects/Ethernet.py
@@ -1,5 +1,7 @@
+from m5.SimObject import SimObject
+from m5.params import *
+from m5.proxy import *
from m5 import build_env
-from m5.config import *
from Device import DmaDevice
from Pci import PciDevice, PciConfigData
diff --git a/src/python/m5/objects/FUPool.py b/src/python/m5/objects/FUPool.py
index cbf1089cf..4b4be79a6 100644
--- a/src/python/m5/objects/FUPool.py
+++ b/src/python/m5/objects/FUPool.py
@@ -1,4 +1,5 @@
-from m5.config import *
+from m5.SimObject import SimObject
+from m5.params import *
class FUPool(SimObject):
type = 'FUPool'
diff --git a/src/python/m5/objects/FuncUnit.py b/src/python/m5/objects/FuncUnit.py
index f61590ae9..f0ad55f7a 100644
--- a/src/python/m5/objects/FuncUnit.py
+++ b/src/python/m5/objects/FuncUnit.py
@@ -1,4 +1,5 @@
-from m5.config import *
+from m5.SimObject import SimObject
+from m5.params import *
class OpType(Enum):
vals = ['(null)', 'IntAlu', 'IntMult', 'IntDiv', 'FloatAdd',
diff --git a/src/python/m5/objects/Ide.py b/src/python/m5/objects/Ide.py
index a8bd4ac5a..69681bdbd 100644
--- a/src/python/m5/objects/Ide.py
+++ b/src/python/m5/objects/Ide.py
@@ -1,4 +1,5 @@
-from m5.config import *
+from m5.SimObject import SimObject
+from m5.params import *
from Pci import PciDevice, PciConfigData
class IdeID(Enum): vals = ['master', 'slave']
diff --git a/src/python/m5/objects/IntrControl.py b/src/python/m5/objects/IntrControl.py
index 514c3fc62..95be0f4df 100644
--- a/src/python/m5/objects/IntrControl.py
+++ b/src/python/m5/objects/IntrControl.py
@@ -1,4 +1,6 @@
-from m5.config import *
+from m5.SimObject import SimObject
+from m5.params import *
+from m5.proxy import *
class IntrControl(SimObject):
type = 'IntrControl'
cpu = Param.BaseCPU(Parent.any, "the cpu")
diff --git a/src/python/m5/objects/MemObject.py b/src/python/m5/objects/MemObject.py
index d957dae17..8982d553d 100644
--- a/src/python/m5/objects/MemObject.py
+++ b/src/python/m5/objects/MemObject.py
@@ -1,4 +1,5 @@
-from m5.config import *
+from m5.SimObject import SimObject
+from m5.SimObject import SimObject
class MemObject(SimObject):
type = 'MemObject'
diff --git a/src/python/m5/objects/MemTest.py b/src/python/m5/objects/MemTest.py
index 9916d7cb4..97600768f 100644
--- a/src/python/m5/objects/MemTest.py
+++ b/src/python/m5/objects/MemTest.py
@@ -1,4 +1,5 @@
-from m5.config import *
+from m5.SimObject import SimObject
+from m5.params import *
class MemTest(SimObject):
type = 'MemTest'
cache = Param.BaseCache("L1 cache")
diff --git a/src/python/m5/objects/O3CPU.py b/src/python/m5/objects/O3CPU.py
index 900bbf28c..5100c7ccb 100644
--- a/src/python/m5/objects/O3CPU.py
+++ b/src/python/m5/objects/O3CPU.py
@@ -1,5 +1,6 @@
+from m5.params import *
+from m5.proxy import *
from m5 import build_env
-from m5.config import *
from BaseCPU import BaseCPU
from Checker import O3Checker
diff --git a/src/python/m5/objects/OzoneCPU.py b/src/python/m5/objects/OzoneCPU.py
index 88fb63c74..8f25d77ed 100644
--- a/src/python/m5/objects/OzoneCPU.py
+++ b/src/python/m5/objects/OzoneCPU.py
@@ -1,5 +1,5 @@
+from m5.params import *
from m5 import build_env
-from m5.config import *
from BaseCPU import BaseCPU
class DerivOzoneCPU(BaseCPU):
diff --git a/src/python/m5/objects/Pci.py b/src/python/m5/objects/Pci.py
index cc0d1cf4a..7c239d069 100644
--- a/src/python/m5/objects/Pci.py
+++ b/src/python/m5/objects/Pci.py
@@ -1,4 +1,6 @@
-from m5.config import *
+from m5.SimObject import SimObject
+from m5.params import *
+from m5.proxy import *
from Device import BasicPioDevice, DmaDevice, PioDevice
class PciConfigData(SimObject):
diff --git a/src/python/m5/objects/PhysicalMemory.py b/src/python/m5/objects/PhysicalMemory.py
index bc427aa88..dd3ffd651 100644
--- a/src/python/m5/objects/PhysicalMemory.py
+++ b/src/python/m5/objects/PhysicalMemory.py
@@ -1,4 +1,5 @@
-from m5.config import *
+from m5.params import *
+from m5.proxy import *
from MemObject import *
class PhysicalMemory(MemObject):
diff --git a/src/python/m5/objects/Platform.py b/src/python/m5/objects/Platform.py
index 89fee9991..ab2083eea 100644
--- a/src/python/m5/objects/Platform.py
+++ b/src/python/m5/objects/Platform.py
@@ -1,4 +1,6 @@
-from m5.config import *
+from m5.SimObject import SimObject
+from m5.params import *
+from m5.proxy import *
class Platform(SimObject):
type = 'Platform'
abstract = True
diff --git a/src/python/m5/objects/Process.py b/src/python/m5/objects/Process.py
index 0091d8654..08f8b6bce 100644
--- a/src/python/m5/objects/Process.py
+++ b/src/python/m5/objects/Process.py
@@ -1,4 +1,6 @@
-from m5.config import *
+from m5.SimObject import SimObject
+from m5.params import *
+from m5.proxy import *
class Process(SimObject):
type = 'Process'
abstract = True
diff --git a/src/python/m5/objects/Repl.py b/src/python/m5/objects/Repl.py
index 8e9f1094f..10892cf6f 100644
--- a/src/python/m5/objects/Repl.py
+++ b/src/python/m5/objects/Repl.py
@@ -1,4 +1,5 @@
-from m5.config import *
+from m5.SimObject import SimObject
+from m5.params import *
class Repl(SimObject):
type = 'Repl'
abstract = True
diff --git a/src/python/m5/objects/Root.py b/src/python/m5/objects/Root.py
index 33dd22620..f01fc06c4 100644
--- a/src/python/m5/objects/Root.py
+++ b/src/python/m5/objects/Root.py
@@ -1,4 +1,5 @@
-from m5.config import *
+from m5.SimObject import SimObject
+from m5.params import *
from Serialize import Serialize
from Statistics import Statistics
from Trace import Trace
diff --git a/src/python/m5/objects/SimConsole.py b/src/python/m5/objects/SimConsole.py
index 9e1452c6d..bdd7f246d 100644
--- a/src/python/m5/objects/SimConsole.py
+++ b/src/python/m5/objects/SimConsole.py
@@ -1,4 +1,6 @@
-from m5.config import *
+from m5.SimObject import SimObject
+from m5.params import *
+from m5.proxy import *
class ConsoleListener(SimObject):
type = 'ConsoleListener'
port = Param.TcpPort(3456, "listen port")
diff --git a/src/python/m5/objects/SimpleDisk.py b/src/python/m5/objects/SimpleDisk.py
index 44ef709af..099a77dbb 100644
--- a/src/python/m5/objects/SimpleDisk.py
+++ b/src/python/m5/objects/SimpleDisk.py
@@ -1,4 +1,6 @@
-from m5.config import *
+from m5.SimObject import SimObject
+from m5.params import *
+from m5.proxy import *
class SimpleDisk(SimObject):
type = 'SimpleDisk'
disk = Param.DiskImage("Disk Image")
diff --git a/src/python/m5/objects/SimpleOzoneCPU.py b/src/python/m5/objects/SimpleOzoneCPU.py
index 5d968cab0..193f31b0f 100644
--- a/src/python/m5/objects/SimpleOzoneCPU.py
+++ b/src/python/m5/objects/SimpleOzoneCPU.py
@@ -1,5 +1,5 @@
+from m5.params import *
from m5 import build_env
-from m5.config import *
from BaseCPU import BaseCPU
class SimpleOzoneCPU(BaseCPU):
diff --git a/src/python/m5/objects/System.py b/src/python/m5/objects/System.py
index 386f39277..bc2a002cb 100644
--- a/src/python/m5/objects/System.py
+++ b/src/python/m5/objects/System.py
@@ -1,5 +1,7 @@
+from m5.SimObject import SimObject
+from m5.params import *
+from m5.proxy import *
from m5 import build_env
-from m5.config import *
class MemoryMode(Enum): vals = ['invalid', 'atomic', 'timing']
diff --git a/src/python/m5/objects/Tsunami.py b/src/python/m5/objects/Tsunami.py
index 0b5ff9e7d..0b53153a0 100644
--- a/src/python/m5/objects/Tsunami.py
+++ b/src/python/m5/objects/Tsunami.py
@@ -1,4 +1,5 @@
-from m5.config import *
+from m5.params import *
+from m5.proxy import *
from Device import BasicPioDevice
from Platform import Platform
from AlphaConsole import AlphaConsole
diff --git a/src/python/m5/objects/Uart.py b/src/python/m5/objects/Uart.py
index 8e1fd1a37..62062c6b1 100644
--- a/src/python/m5/objects/Uart.py
+++ b/src/python/m5/objects/Uart.py
@@ -1,5 +1,6 @@
+from m5.params import *
+from m5.proxy import *
from m5 import build_env
-from m5.config import *
from Device import BasicPioDevice
class Uart(BasicPioDevice):
diff --git a/src/python/m5/params.py b/src/python/m5/params.py
index eb30e5c4d..db11b9cff 100644
--- a/src/python/m5/params.py
+++ b/src/python/m5/params.py
@@ -46,6 +46,7 @@
import sys, inspect, copy
import convert
+from util import *
# Dummy base class to identify types that are legitimate for SimObject
# parameters.
@@ -100,13 +101,14 @@ class ParamDesc(object):
def __getattr__(self, attr):
if attr == 'ptype':
try:
- ptype = eval(self.ptype_str, m5.objects.__dict__)
+ ptype = eval(self.ptype_str, objects.__dict__)
if not isinstance(ptype, type):
- panic("Param qualifier is not a type: %s" % self.ptype)
+ raise NameError
self.ptype = ptype
return ptype
except NameError:
- pass
+ raise TypeError, \
+ "Param qualifier '%s' is not a type" % self.ptype_str
raise AttributeError, "'%s' object has no attribute '%s'" % \
(type(self).__name__, attr)
@@ -120,7 +122,7 @@ class ParamDesc(object):
return value
if isinstance(value, self.ptype):
return value
- if isNullPointer(value) and issubclass(self.ptype, SimObject):
+ if isNullPointer(value) and isSimObjectClass(self.ptype):
return value
return self.ptype(value)
@@ -305,7 +307,7 @@ class CheckedInt(NumericParamValue):
def __init__(self, value):
if isinstance(value, str):
- self.value = toInteger(value)
+ self.value = convert.toInteger(value)
elif isinstance(value, (int, long, float)):
self.value = long(value)
self._check()
@@ -340,7 +342,7 @@ class MemorySize(CheckedInt):
if isinstance(value, MemorySize):
self.value = value.value
else:
- self.value = toMemorySize(value)
+ self.value = convert.toMemorySize(value)
self._check()
class MemorySize32(CheckedInt):
@@ -350,7 +352,7 @@ class MemorySize32(CheckedInt):
if isinstance(value, MemorySize):
self.value = value.value
else:
- self.value = toMemorySize(value)
+ self.value = convert.toMemorySize(value)
self._check()
class Addr(CheckedInt):
@@ -363,7 +365,7 @@ class Addr(CheckedInt):
self.value = value.value
else:
try:
- self.value = toMemorySize(value)
+ self.value = convert.toMemorySize(value)
except TypeError:
self.value = long(value)
self._check()
@@ -430,7 +432,7 @@ class Bool(ParamValue):
cxx_type = 'bool'
def __init__(self, value):
try:
- self.value = toBool(value)
+ self.value = convert.toBool(value)
except TypeError:
self.value = bool(value)
@@ -586,10 +588,10 @@ def getLatency(value):
return 1 / value.value
elif isinstance(value, str):
try:
- return toLatency(value)
+ return convert.toLatency(value)
except ValueError:
try:
- return 1 / toFrequency(value)
+ return 1 / convert.toFrequency(value)
except ValueError:
pass # fall through
raise ValueError, "Invalid Frequency/Latency value '%s'" % value
@@ -678,7 +680,7 @@ class Clock(ParamValue):
class NetworkBandwidth(float,ParamValue):
cxx_type = 'float'
def __new__(cls, value):
- val = toNetworkBandwidth(value) / 8.0
+ val = convert.toNetworkBandwidth(value) / 8.0
return super(cls, NetworkBandwidth).__new__(cls, val)
def __str__(self):
@@ -690,7 +692,7 @@ class NetworkBandwidth(float,ParamValue):
class MemoryBandwidth(float,ParamValue):
cxx_type = 'float'
def __new__(self, value):
- val = toMemoryBandwidth(value)
+ val = convert.toMemoryBandwidth(value)
return super(cls, MemoryBandwidth).__new__(cls, val)
def __str__(self):
@@ -703,6 +705,36 @@ class MemoryBandwidth(float,ParamValue):
# "Constants"... handy aliases for various values.
#
+# Special class for NULL pointers. Note the special check in
+# make_param_value() above that lets these be assigned where a
+# SimObject is required.
+# only one copy of a particular node
+class NullSimObject(object):
+ __metaclass__ = Singleton
+
+ def __call__(cls):
+ return cls
+
+ def _instantiate(self, parent = None, path = ''):
+ pass
+
+ def ini_str(self):
+ return 'Null'
+
+ def unproxy(self, base):
+ return self
+
+ def set_path(self, parent, name):
+ pass
+ def __str__(self):
+ return 'Null'
+
+# The only instance you'll ever need...
+NULL = NullSimObject()
+
+def isNullPointer(value):
+ return isinstance(value, NullSimObject)
+
# Some memory range specifications use this as a default upper bound.
MaxAddr = Addr.max
MaxTick = Tick.max
@@ -821,11 +853,11 @@ __all__ = ['Param', 'VectorParam',
'NetworkBandwidth', 'MemoryBandwidth',
'Range', 'AddrRange', 'TickRange',
'MaxAddr', 'MaxTick', 'AllMemory',
- 'Null', 'NULL',
- 'NextEthernetAddr',
+ 'NextEthernetAddr', 'NULL',
'Port', 'VectorPort']
# see comment on imports at end of __init__.py.
-from SimObject import SimObject, isSimObject, isSimObjectSequence, \
- isNullPointer
+from SimObject import isSimObject, isSimObjectSequence, isSimObjectClass
import proxy
+import objects
+import cc_main