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| author | Kevin Lim <ktlim@umich.edu> | 2007-03-29 12:25:47 -0400 |
|---|---|---|
| committer | Kevin Lim <ktlim@umich.edu> | 2007-03-29 12:25:47 -0400 |
| commit | 5c3f724174dbad18041858fde6418207abfc1d27 (patch) | |
| tree | 502328c0affdeadf19caeea0d702640a68d3dcb8 /src/python/m5 | |
| parent | 80af6530f65551c7f47bf62f10093e6e420b47f2 (diff) | |
| download | gem5-5c3f724174dbad18041858fde6418207abfc1d27.tar.xz | |
Override addPrivateSplitL1Caches function in order to automatically set the tgts_per_mshr of the caches to 20. This is needed otherwise things will potentially lock up when using the O3CPU because the caches can run out of targets, and then not respond.
Remove this hack once the caches eventually get fixed.
--HG--
extra : convert_revision : 8c61ac1b6182f57ebbe3bcfeddb5a4f4334d7bc0
Diffstat (limited to 'src/python/m5')
| -rw-r--r-- | src/python/m5/objects/O3CPU.py | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/python/m5/objects/O3CPU.py b/src/python/m5/objects/O3CPU.py index 20eef383f..5fba4e96f 100644 --- a/src/python/m5/objects/O3CPU.py +++ b/src/python/m5/objects/O3CPU.py @@ -116,3 +116,8 @@ class DerivO3CPU(BaseCPU): smtROBPolicy = Param.String("SMT ROB Sharing Policy") smtROBThreshold = Param.String("SMT ROB Threshold Sharing Parameter") smtCommitPolicy = Param.String("SMT Commit Policy") + + def addPrivateSplitL1Caches(self, ic, dc): + BaseCPU.addPrivateSplitL1Caches(self, ic, dc) + self.icache.tgts_per_mshr = 20 + self.dcache.tgts_per_mshr = 20 |