summaryrefslogtreecommitdiff
path: root/src/python/m5
diff options
context:
space:
mode:
authorGabe Black <gblack@eecs.umich.edu>2010-07-15 02:11:56 -0700
committerGabe Black <gblack@eecs.umich.edu>2010-07-15 02:11:56 -0700
commit8cec87056824782e061eac152b83432899d9b6d9 (patch)
tree58033e5bee79ae6c446efc763539ae769776ebbb /src/python/m5
parent4e3183cb1e5d4081fa7688bf89f8c776c52ec393 (diff)
downloadgem5-8cec87056824782e061eac152b83432899d9b6d9.tar.xz
ARM: Make an SRS instruction with a bad mode cause an undefined instruction fault.
Diffstat (limited to 'src/python/m5')
0 files changed, 0 insertions, 0 deletions