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| author | Ron Dreslinski <rdreslin@umich.edu> | 2006-10-18 13:34:52 -0400 |
|---|---|---|
| committer | Ron Dreslinski <rdreslin@umich.edu> | 2006-10-18 13:34:52 -0400 |
| commit | 63c2a782d60dffaf7150ed0799767b215bbce6fb (patch) | |
| tree | bf576dc58c45031b5a2592f9574ac400876cd070 /src/python/m5 | |
| parent | 9c582c7e144aef0bfc9d14bb4690d56d1688496a (diff) | |
| parent | 0e2561710b44f811a5e179935d54ef240013d03e (diff) | |
| download | gem5-63c2a782d60dffaf7150ed0799767b215bbce6fb.tar.xz | |
Merge zizzer:/bk/newmem
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
--HG--
extra : convert_revision : 9e47881686a6c060fa28e7edfd9a0b556099bf30
Diffstat (limited to 'src/python/m5')
| -rw-r--r-- | src/python/m5/objects/AlphaConsole.py | 2 | ||||
| -rw-r--r-- | src/python/m5/objects/BaseCache.py | 1 | ||||
| -rw-r--r-- | src/python/m5/objects/IntrControl.py | 2 |
3 files changed, 2 insertions, 3 deletions
diff --git a/src/python/m5/objects/AlphaConsole.py b/src/python/m5/objects/AlphaConsole.py index 1c71493b1..f968aaa40 100644 --- a/src/python/m5/objects/AlphaConsole.py +++ b/src/python/m5/objects/AlphaConsole.py @@ -4,7 +4,7 @@ from Device import BasicPioDevice class AlphaConsole(BasicPioDevice): type = 'AlphaConsole' - cpu = Param.BaseCPU(Parent.any, "Processor") + cpu = Param.BaseCPU(Parent.cpu[0], "Processor") disk = Param.SimpleDisk("Simple Disk") sim_console = Param.SimConsole(Parent.any, "The Simulator Console") system = Param.AlphaSystem(Parent.any, "system object") diff --git a/src/python/m5/objects/BaseCache.py b/src/python/m5/objects/BaseCache.py index db58a177f..773a11bea 100644 --- a/src/python/m5/objects/BaseCache.py +++ b/src/python/m5/objects/BaseCache.py @@ -14,7 +14,6 @@ class BaseCache(MemObject): "This cache connects to a compressed memory") compression_latency = Param.Latency('0ns', "Latency in cycles of compression algorithm") - do_copy = Param.Bool(False, "perform fast copies in the cache") hash_delay = Param.Int(1, "time in cycles of hash access") lifo = Param.Bool(False, "whether this NIC partition should use LIFO repl. policy") diff --git a/src/python/m5/objects/IntrControl.py b/src/python/m5/objects/IntrControl.py index 95be0f4df..a7cf5cc84 100644 --- a/src/python/m5/objects/IntrControl.py +++ b/src/python/m5/objects/IntrControl.py @@ -3,4 +3,4 @@ from m5.params import * from m5.proxy import * class IntrControl(SimObject): type = 'IntrControl' - cpu = Param.BaseCPU(Parent.any, "the cpu") + cpu = Param.BaseCPU(Parent.cpu[0], "the cpu") |