diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2006-11-16 14:41:56 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2006-11-16 14:41:56 -0500 |
| commit | 14ebaa1eccff4032d59147783e98e07b81b5f1ae (patch) | |
| tree | 4c738d02f4876cb394d0f9510d08380a6f5384c1 /src/python/m5 | |
| parent | ac2c7967f69e3ffd29a1ed04a15838073dc060de (diff) | |
| parent | dbdf2f14ae6b586efd31b73aa4548a38ecee263f (diff) | |
| download | gem5-14ebaa1eccff4032d59147783e98e07b81b5f1ae.tar.xz | |
Merge zizzer.eecs.umich.edu:/bk/newmem/
into zower.eecs.umich.edu:/home/gblack/m5/newmemmemops
--HG--
extra : convert_revision : c49b760eac758dbde30867cb638fcb3b790f4721
Diffstat (limited to 'src/python/m5')
| -rw-r--r-- | src/python/m5/objects/BaseCPU.py | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/python/m5/objects/BaseCPU.py b/src/python/m5/objects/BaseCPU.py index 2f702a4bf..8037c90af 100644 --- a/src/python/m5/objects/BaseCPU.py +++ b/src/python/m5/objects/BaseCPU.py @@ -47,6 +47,7 @@ class BaseCPU(SimObject): "defer registration with system (for sampling)") clock = Param.Clock(Parent.clock, "clock speed") + phase = Param.Latency("0ns", "clock phase") _mem_ports = [] |