Get SPARC to the point that it starts running. Add ability to load the ROM bin files, cleanup lockstep printing a bit

Since we don't have a platform yet, you need to comment out the default responder stuff in Bus.py to make it work.

SConstruct:
    Add TARGET_ISA to the list of environment variables that end up in the build_env for python
configs/common/FSConfig.py:
    add a simple SPARC system to being testing with, you'll need to change makeLinuxAlphaSystem to makeSparcSystem in fs.py for now
src/SConscript:
    add a raw file object, at least until we get more info about how to compile openboot properly
src/arch/sparc/system.cc:
src/arch/sparc/system.hh:
    add parameters for ROM files (OBP/Reset/Hypervisor), a ROM, load files into ROM
src/base/loader/object_file.cc:
src/base/loader/object_file.hh:
    add option to try raw when nothing works
src/cpu/exetrace.cc:
    cleanup lockstep printing a little bit
src/cpu/m5legion_interface.h:
    change the instruction to be 32 bits because it is
src/mem/physical.cc:
    fix assert that doesn't work if memory starts somewhere above 0
src/python/m5/objects/BaseCPU.py:
    Add if statement to choose between sparc tlbs and alpha tlbs
src/python/m5/objects/System.py:
    Add a sparc system that sets the rom addresses correctly
src/python/m5/params.py:
    add the ability to add Addr() together

--HG--
extra : convert_revision : bbbd8a56134f2dda2728091f740e2f7119b0c4af

4 files changed, 49 insertions, 2 deletions

diff --git a/src/python/m5/objects/BaseCPU.py b/src/python/m5/objects/BaseCPU.py
index 4e34e8a4e..b6e05627d 100644
--- a/src/python/m5/objects/BaseCPU.py
+++ b/src/python/m5/objects/BaseCPU.py
@@ -3,7 +3,9 @@ from m5.params import *
 from m5.proxy import *
 from m5 import build_env
 from AlphaTLB import AlphaDTB, AlphaITB
+from SparcTLB import SparcDTB, SparcITB
 from Bus import Bus
+import sys
 
 class BaseCPU(SimObject):
     type = 'BaseCPU'
@@ -13,8 +15,15 @@ class BaseCPU(SimObject):
     cpu_id = Param.Int("CPU identifier")
 
     if build_env['FULL_SYSTEM']:
-        dtb = Param.AlphaDTB(AlphaDTB(), "Data TLB")
-        itb = Param.AlphaITB(AlphaITB(), "Instruction TLB")
+        if build_env['TARGET_ISA'] == 'sparc':
+            dtb = Param.SparcDTB(SparcDTB(), "Data TLB")
+            itb = Param.SparcITB(SparcITB(), "Instruction TLB")
+        elif build_env['TARGET_ISA'] == 'alpha':
+            dtb = Param.AlphaDTB(AlphaDTB(), "Data TLB")
+            itb = Param.AlphaITB(AlphaITB(), "Instruction TLB")
+        else:
+            print "Unknown architecture, can't pick TLBs"
+            sys.exit(1)
     else:
         workload = VectorParam.Process("processes to run")
 
diff --git a/src/python/m5/objects/SparcTLB.py b/src/python/m5/objects/SparcTLB.py
new file mode 100644
index 000000000..de732e8de
--- /dev/null
+++ b/src/python/m5/objects/SparcTLB.py
@@ -0,0 +1,14 @@
+from m5.SimObject import SimObject
+from m5.params import *
+class SparcTLB(SimObject):
+    type = 'SparcTLB'
+    abstract = True
+    size = Param.Int("TLB size")
+
+class SparcDTB(SparcTLB):
+    type = 'SparcDTB'
+    size = 64
+
+class SparcITB(SparcTLB):
+    type = 'SparcITB'
+    size = 48
diff --git a/src/python/m5/objects/System.py b/src/python/m5/objects/System.py
index e7dd1bc60..908c3d4ad 100644
--- a/src/python/m5/objects/System.py
+++ b/src/python/m5/objects/System.py
@@ -2,6 +2,7 @@ from m5.SimObject import SimObject
 from m5.params import *
 from m5.proxy import *
 from m5 import build_env
+from PhysicalMemory import *
 
 class MemoryMode(Enum): vals = ['invalid', 'atomic', 'timing']
 
@@ -24,3 +25,21 @@ class AlphaSystem(System):
     pal = Param.String("file that contains palcode")
     system_type = Param.UInt64("Type of system we are emulating")
     system_rev = Param.UInt64("Revision of system we are emulating")
+
+class SparcSystem(System):
+    type = 'SparcSystem'
+    _rom_base = 0xfff0000000
+    # ROM for OBP/Reset/Hypervisor
+    rom = Param.PhysicalMemory(PhysicalMemory(range = AddrRange(_rom_base, size = '8MB')),
+            "Memory to hold the ROM data")
+
+    reset_addr = Param.Addr(_rom_base, "Address to load ROM at")
+    hypervisor_addr = Param.Addr(Addr('64kB') + _rom_base,
+                                 "Address to load hypervisor at")
+    openboot_addr = Param.Addr(Addr('512kB') + _rom_base,
+                               "Address to load openboot at")
+
+    reset_bin = Param.String("file that contains the reset code")
+    hypervisor_bin = Param.String("file that contains the hypervisor code")
+    openboot_bin = Param.String("file that contains the openboot code")
+
diff --git a/src/python/m5/params.py b/src/python/m5/params.py
index 93d784181..4b5953bcb 100644
--- a/src/python/m5/params.py
+++ b/src/python/m5/params.py
@@ -369,6 +369,11 @@ class Addr(CheckedInt):
             except TypeError:
                 self.value = long(value)
         self._check()
+    def __add__(self, other):
+        if isinstance(other, Addr):
+            return self.value + other.value
+        else:
+            return self.value + other
 
 
 class MetaRange(type):