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| author | Ali Saidi <saidi@eecs.umich.edu> | 2006-12-06 19:25:53 -0500 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2006-12-06 19:25:53 -0500 |
| commit | 03be92f23b36ba69bfee179f97cd5af23c0f6e2c (patch) | |
| tree | c289dbf19cbccc249340e4e6f8f8129ec2b19d41 /src/python/m5 | |
| parent | ecbb8debf672ee1463115319a24384eeb6b98ee3 (diff) | |
| download | gem5-03be92f23b36ba69bfee179f97cd5af23c0f6e2c.tar.xz | |
Handle access to ASI_QUEUE
Add function for interrupt ASIs
add all the new MISCREGs to the copyMiscRegs() file
src/arch/sparc/asi.cc:
src/arch/sparc/asi.hh:
Add function for interrupt ASIs
src/arch/sparc/miscregfile.cc:
src/arch/sparc/miscregfile.hh:
Add QUEUE asi/misc registers
src/arch/sparc/regfile.cc:
add all the new MISCREGs to the copyMiscRegs() file
src/arch/sparc/tlb.cc:
Handle access to ASI_QUEUE
--HG--
extra : convert_revision : 7a14450485816e6ee3bc8c80b462a13e1edf0ba0
Diffstat (limited to 'src/python/m5')
0 files changed, 0 insertions, 0 deletions