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| author | Kevin Lim <ktlim@umich.edu> | 2006-07-06 14:54:09 -0400 |
|---|---|---|
| committer | Kevin Lim <ktlim@umich.edu> | 2006-07-06 14:54:09 -0400 |
| commit | c8a37ce71514de9362640e8cb18c1744f0e2f83b (patch) | |
| tree | 70eb71e46428c20bd6a44eed1d08a019abb70e25 /src/python/m5 | |
| parent | 05eef5ee1569f7a1c399a2b358a11323e88a48f8 (diff) | |
| parent | 4b741100714c6f20749f344ddd4b16459f28df72 (diff) | |
| download | gem5-c8a37ce71514de9362640e8cb18c1744f0e2f83b.tar.xz | |
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge
--HG--
extra : convert_revision : 0c4fbbe0826358a6a58f844bec34ce830ffd4ced
Diffstat (limited to 'src/python/m5')
| -rw-r--r-- | src/python/m5/objects/Bus.py | 1 | ||||
| -rw-r--r-- | src/python/m5/objects/Pci.py | 10 |
2 files changed, 8 insertions, 3 deletions
diff --git a/src/python/m5/objects/Bus.py b/src/python/m5/objects/Bus.py index 019e15034..e0278e6c3 100644 --- a/src/python/m5/objects/Bus.py +++ b/src/python/m5/objects/Bus.py @@ -4,4 +4,5 @@ from MemObject import MemObject class Bus(MemObject): type = 'Bus' port = VectorPort("vector port for connecting devices") + default = Port("Default port for requests that aren't handeled by a device.") bus_id = Param.Int(0, "blah") diff --git a/src/python/m5/objects/Pci.py b/src/python/m5/objects/Pci.py index 9e1e91b13..29014bb37 100644 --- a/src/python/m5/objects/Pci.py +++ b/src/python/m5/objects/Pci.py @@ -1,5 +1,5 @@ from m5.config import * -from Device import BasicPioDevice, DmaDevice +from Device import BasicPioDevice, DmaDevice, PioDevice class PciConfigData(SimObject): type = 'PciConfigData' @@ -38,18 +38,22 @@ class PciConfigData(SimObject): MaximumLatency = Param.UInt8(0x00, "Maximum Latency") MinimumGrant = Param.UInt8(0x00, "Minimum Grant") -class PciConfigAll(BasicPioDevice): +class PciConfigAll(PioDevice): type = 'PciConfigAll' + pio_latency = Param.Tick(1, "Programmed IO latency in simticks") + bus = Param.UInt8(0x00, "PCI bus to act as config space for") + size = Param.MemorySize32('16MB', "Size of config space") + class PciDevice(DmaDevice): type = 'PciDevice' abstract = True + config = Port("PCI configuration space port") pci_bus = Param.Int("PCI bus") pci_dev = Param.Int("PCI device number") pci_func = Param.Int("PCI function code") pio_latency = Param.Tick(1, "Programmed IO latency in simticks") configdata = Param.PciConfigData(Parent.any, "PCI Config data") - configspace = Param.PciConfigAll(Parent.any, "PCI Configspace") class PciFake(PciDevice): type = 'PciFake' |