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| author | Ron Dreslinski <rdreslin@umich.edu> | 2006-10-20 13:01:21 -0400 |
|---|---|---|
| committer | Ron Dreslinski <rdreslin@umich.edu> | 2006-10-20 13:01:21 -0400 |
| commit | 28e9641c2cf063d8ee1eba9f440dfcda9c82d965 (patch) | |
| tree | 27d82f9251fe5b6eb5d4daa94c6b2af00f324229 /src/python/m5 | |
| parent | 780aa0a0ebb765781a31d0fb58257b1efb1f324a (diff) | |
| download | gem5-28e9641c2cf063d8ee1eba9f440dfcda9c82d965.tar.xz | |
Use fixPacket function everywhere.
Fix fixPacket assert function.
Stop timing port from forwarding the request if a response was found in its queue on a read.
src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
src/python/m5/objects/MemTest.py:
Add parameter to configure what percentage of mem accesses are functional
src/mem/cache/base_cache.cc:
src/mem/cache/cache_impl.hh:
Use fix Packet function
src/mem/packet.cc:
Fix an assert that was checking the wrong thing
src/mem/tport.cc:
Properly detect if we need to do the access to the functional device
--HG--
extra : convert_revision : 447cc1a9a65ddd2a41e937fb09dc0e7c74e9c75e
Diffstat (limited to 'src/python/m5')
| -rw-r--r-- | src/python/m5/objects/MemTest.py | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/python/m5/objects/MemTest.py b/src/python/m5/objects/MemTest.py index 83399be80..1219ddd4d 100644 --- a/src/python/m5/objects/MemTest.py +++ b/src/python/m5/objects/MemTest.py @@ -13,6 +13,7 @@ class MemTest(SimObject): percent_reads = Param.Percent(65, "target read percentage") percent_source_unaligned = Param.Percent(50, "percent of copy source address that are unaligned") + percent_functional = Param.Percent(50, "percent of access that are functional") percent_uncacheable = Param.Percent(10, "target uncacheable percentage") progress_interval = Param.Counter(1000000, |