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author | Kevin Lim <ktlim@umich.edu> | 2006-10-08 00:53:41 -0400 |
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committer | Kevin Lim <ktlim@umich.edu> | 2006-10-08 00:53:41 -0400 |
commit | d48ea81ba2c4034936ada75bd4bac28640c53174 (patch) | |
tree | 5ecb00de2f00dfe0d9a93dc393f3a725578443fb /src/python/m5 | |
parent | c0e53b6d4c19bffc2ae9d960f5fffd7510a6ec42 (diff) | |
download | gem5-d48ea81ba2c4034936ada75bd4bac28640c53174.tar.xz |
Updates to O3 CPU. It should now work in FS mode, although sampling still has a bug.
src/cpu/o3/commit_impl.hh:
Fixes for compile and sampling.
src/cpu/o3/cpu.cc:
Deallocate and activate threads properly. Also hopefully fix being able to use caches while switching over.
src/cpu/o3/cpu.hh:
Fixes for deallocating and activating threads.
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/lsq_unit.hh:
Handle getting back a BadAddress result from the access.
src/cpu/o3/iew_impl.hh:
More debug output.
src/cpu/o3/lsq_unit_impl.hh:
Fixup store conditional handling (still a bit of a hack, but works now).
Also handle getting back a BadAddress result from the access.
src/cpu/o3/thread_context_impl.hh:
Deallocate context now records if the context should be fully removed.
--HG--
extra : convert_revision : 55f81660602d0e25367ce1f5b0b9cfc62abe7bf9
Diffstat (limited to 'src/python/m5')
0 files changed, 0 insertions, 0 deletions