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authorSteve Reinhardt ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E%2C%20Ali%20Saidi%20%3CAli.Saidi%40ARM.com%3E) <stever@gmail.com>2013-11-25 11:21:00 -0600
committerSteve Reinhardt ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E%2C%20Ali%20Saidi%20%3CAli.Saidi%40ARM.com%3E) <stever@gmail.com>2013-11-25 11:21:00 -0600
commitde366a16f11b7e27a5b5e064a2a773052568428e (patch)
tree9bed0ebc9801c118e0f17702a979a659a59a67df /src/python/m5
parent8a53da22c2f07aed924a45ab296f7468d842d7f6 (diff)
downloadgem5-de366a16f11b7e27a5b5e064a2a773052568428e.tar.xz
sim: simulate with multiple threads and event queues
This patch adds support for simulating with multiple threads, each of which operates on an event queue. Each sim object specifies which eventq is would like to be on. A custom barrier implementation is being added using which eventqs synchronize. The patch was tested in two different configurations: 1. ruby_network_test.py: in this simulation L1 cache controllers receive requests from the cpu. The requests are replied to immediately without any communication taking place with any other level. 2. twosys-tsunami-simple-atomic: this configuration simulates a client-server system which are connected by an ethernet link. We still lack the ability to communicate using message buffers or ports. But other things like simulation start and end, synchronizing after every quantum are working. Committed by: Nilay Vaish
Diffstat (limited to 'src/python/m5')
-rw-r--r--src/python/m5/SimObject.py23
-rw-r--r--src/python/m5/event.py12
-rw-r--r--src/python/m5/main.py4
-rw-r--r--src/python/m5/simulate.py13
4 files changed, 34 insertions, 18 deletions
diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py
index 14499759c..9b60dfef6 100644
--- a/src/python/m5/SimObject.py
+++ b/src/python/m5/SimObject.py
@@ -11,7 +11,8 @@
# modified or unmodified, in source code or in binary form.
#
# Copyright (c) 2004-2006 The Regents of The University of Michigan
-# Copyright (c) 2010 Advanced Micro Devices, Inc.
+# Copyright (c) 2010-20013 Advanced Micro Devices, Inc.
+# Copyright (c) 2013 Mark D. Hill and David A. Wood
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
@@ -528,8 +529,6 @@ struct PyObject;
#endif
#include <string>
-
-class EventQueue;
''')
for param in params:
param.cxx_predecls(code)
@@ -558,16 +557,11 @@ class EventQueue;
code.indent()
if cls == SimObject:
code('''
- SimObjectParams()
- {
- extern EventQueue mainEventQueue;
- eventq = &mainEventQueue;
- }
+ SimObjectParams() {}
virtual ~SimObjectParams() {}
std::string name;
PyObject *pyobj;
- EventQueue *eventq;
''')
for param in params:
param.cxx_decl(code)
@@ -582,6 +576,14 @@ class EventQueue;
return code
+# This *temporary* definition is required to support calls from the
+# SimObject class definition to the MetaSimObject methods (in
+# particular _set_param, which gets called for parameters with default
+# values defined on the SimObject class itself). It will get
+# overridden by the permanent definition (which requires that
+# SimObject be defined) lower in this file.
+def isSimObjectOrVector(value):
+ return False
# The SimObject class is the root of the special hierarchy. Most of
# the code in this class deals with the configuration hierarchy itself
@@ -592,9 +594,10 @@ class SimObject(object):
__metaclass__ = MetaSimObject
type = 'SimObject'
abstract = True
- cxx_header = "sim/sim_object.hh"
+ cxx_header = "sim/sim_object.hh"
cxx_bases = [ "Drainable", "Serializable" ]
+ eventq_index = Param.UInt32(Parent.eventq_index, "Event Queue Index")
@classmethod
def export_method_swig_predecls(cls, code):
diff --git a/src/python/m5/event.py b/src/python/m5/event.py
index 35095599d..76fc37042 100644
--- a/src/python/m5/event.py
+++ b/src/python/m5/event.py
@@ -1,4 +1,6 @@
# Copyright (c) 2006 The Regents of The University of Michigan
+# Copyright (c) 2013 Advanced Micro Devices, Inc.
+# Copyright (c) 2013 Mark D. Hill and David A. Wood
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
@@ -29,9 +31,9 @@
import m5
import internal.event
-from internal.event import PythonEvent, SimLoopExitEvent as SimExit
+from internal.event import PythonEvent, GlobalSimLoopExitEvent as SimExit
-mainq = internal.event.cvar.mainEventQueue
+mainq = None
def create(obj, priority=None):
if priority is None:
@@ -58,4 +60,10 @@ class ProgressEvent(Event):
print "Progress! Time now %fs" % (m5.curTick()/1e12)
self.eventq.schedule(self, m5.curTick() + self.period)
+def getEventQueue(index):
+ return internal.event.getEventQueue(index)
+
+def setEventQueue(eventq):
+ internal.event.curEventQueue(eventq)
+
__all__ = [ 'create', 'Event', 'ProgressEvent', 'SimExit', 'mainq' ]
diff --git a/src/python/m5/main.py b/src/python/m5/main.py
index 611bc99bb..6a6dfa772 100644
--- a/src/python/m5/main.py
+++ b/src/python/m5/main.py
@@ -190,6 +190,10 @@ def main(*args):
fatal("Tracing is not enabled. Compile with TRACING_ON")
+ # Set the main event queue for the main thread.
+ event.mainq = event.getEventQueue(0)
+ event.setEventQueue(event.mainq)
+
if not os.path.isdir(options.outdir):
os.makedirs(options.outdir)
diff --git a/src/python/m5/simulate.py b/src/python/m5/simulate.py
index 322257139..cbd0fb0d4 100644
--- a/src/python/m5/simulate.py
+++ b/src/python/m5/simulate.py
@@ -147,6 +147,13 @@ def simulate(*args, **kwargs):
for obj in root.descendants(): obj.startup()
need_startup = False
+ # Python exit handlers happen in reverse order.
+ # We want to dump stats last.
+ atexit.register(stats.dump)
+
+ # register our C++ exit callback function with Python
+ atexit.register(internal.core.doExitCleanup)
+
for root in need_resume:
resume(root)
need_resume = []
@@ -157,12 +164,6 @@ def simulate(*args, **kwargs):
def curTick():
return internal.core.curTick()
-# Python exit handlers happen in reverse order. We want to dump stats last.
-atexit.register(stats.dump)
-
-# register our C++ exit callback function with Python
-atexit.register(internal.core.doExitCleanup)
-
# Drain the system in preparation of a checkpoint or memory mode
# switch.
def drain(root):