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| author | Gabe Black <gabeblack@google.com> | 2019-11-05 16:58:14 -0800 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2019-12-27 20:52:13 +0000 |
| commit | 31f376f482cfe2bda130de732f86b1181feea2cd (patch) | |
| tree | 0f8554321e90f809ef3f75dadbfb8acb97a53839 /src/python/marshal.cc | |
| parent | 062686655ed2028d7a42112b7a7649e75e79db2e (diff) | |
| download | gem5-31f376f482cfe2bda130de732f86b1181feea2cd.tar.xz | |
fastmodel: Move ARM but not CortexA76 specific bits to the IRIS TC.
Now that the IRIS thread context can be specific to ARM, some things
which had been pushed to a different level of abstraction can be mvoed
back. This will hopefully allow more code sharing in the future when
other types of CPUs are supported.
Change-Id: Ic3a5f0db53ebe93e18f7507ed71812bce27b6d01
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23788
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/python/marshal.cc')
0 files changed, 0 insertions, 0 deletions