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| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2010-08-17 05:08:50 -0700 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2010-08-17 05:08:50 -0700 |
| commit | 5ea906ba1625266ee80968d70e0c218adedcce9f (patch) | |
| tree | a28387572527f0dac40d677a8320b797dcc2a137 /src/python/swig/sim_object.i | |
| parent | c2cce96a0bb4878a9e6a4ae635096b5ce62e41c3 (diff) | |
| download | gem5-5ea906ba1625266ee80968d70e0c218adedcce9f.tar.xz | |
sim: move iterating over SimObjects into Python.
Diffstat (limited to 'src/python/swig/sim_object.i')
| -rw-r--r-- | src/python/swig/sim_object.i | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/python/swig/sim_object.i b/src/python/swig/sim_object.i index c98e44ec2..8cd8e8beb 100644 --- a/src/python/swig/sim_object.i +++ b/src/python/swig/sim_object.i @@ -50,6 +50,12 @@ class SimObject { Drained }; + void init(); + void regStats(); + void regFormulas(); + void resetStats(); + void startup(); + unsigned int drain(Event *drain_event); void resume(); void switchOut(); |