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| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-09-04 13:22:57 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-09-04 13:22:57 -0400 |
| commit | 19a5b68db7d73542833d94ec8b23cad6daf0a787 (patch) | |
| tree | 589541b322580a54e539e24932d3b4bba05801db /src/python/swig | |
| parent | ea402970185d5df01dbad2c0f41b8d76d2eb01cd (diff) | |
| download | gem5-19a5b68db7d73542833d94ec8b23cad6daf0a787.tar.xz | |
arch: Resurrect the NOISA build target and rename it NULL
This patch makes it possible to once again build gem5 without any
ISA. The main purpose is to enable work around the interconnect and
memory system without having to build any CPU models or device models.
The regress script is updated to include the NULL ISA target. Currently
no regressions make use of it, but all the testers could (and perhaps
should) transition to it.
--HG--
rename : build_opts/NOISA => build_opts/NULL
rename : src/arch/noisa/SConsopts => src/arch/null/SConsopts
rename : src/arch/noisa/cpu_dummy.hh => src/arch/null/cpu_dummy.hh
rename : src/cpu/intr_control.cc => src/cpu/intr_control_noisa.cc
Diffstat (limited to 'src/python/swig')
| -rw-r--r-- | src/python/swig/pyobject.cc | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/src/python/swig/pyobject.cc b/src/python/swig/pyobject.cc index f534623f8..fe849ec88 100644 --- a/src/python/swig/pyobject.cc +++ b/src/python/swig/pyobject.cc @@ -34,16 +34,19 @@ #include "base/inifile.hh" #include "base/output.hh" +#include "config/the_isa.hh" +#if THE_ISA != NULL_ISA #include "dev/etherdevice.hh" #include "dev/etherobject.hh" +#endif #include "mem/mem_object.hh" -#include "mem/port.hh" #include "python/swig/pyobject.hh" #include "sim/full_system.hh" #include "sim/sim_object.hh" using namespace std; +#if THE_ISA != NULL_ISA EtherInt * lookupEthPort(SimObject *so, const std::string &name, int i) { @@ -61,6 +64,7 @@ lookupEthPort(SimObject *so, const std::string &name, int i) p = ed->getEthPort(name, i); return p; } +#endif /** * Connect the described MemObject ports. Called from Python via SWIG. @@ -71,6 +75,7 @@ int connectPorts(SimObject *o1, const std::string &name1, int i1, SimObject *o2, const std::string &name2, int i2) { +#if THE_ISA != NULL_ISA if (FullSystem) { EtherObject *eo1, *eo2; EtherDevice *ed1, *ed2; @@ -92,6 +97,7 @@ connectPorts(SimObject *o1, const std::string &name1, int i1, } } } +#endif MemObject *mo1, *mo2; mo1 = dynamic_cast<MemObject*>(o1); mo2 = dynamic_cast<MemObject*>(o2); |