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| author | Ali Saidi <saidi@eecs.umich.edu> | 2006-08-16 19:01:23 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2006-08-16 19:01:23 -0400 |
| commit | 402fbda3df18ff1e4581d441a7ddd59f006926c0 (patch) | |
| tree | 6d6d7a9c345d29e32343baa73419dd3bbcdc8eb2 /src/python | |
| parent | 759626bdeeff140849d464b1fd3ec668f8169504 (diff) | |
| parent | 2f145ac54ab3a9ed2c00e80460a10782da895604 (diff) | |
| download | gem5-402fbda3df18ff1e4581d441a7ddd59f006926c0.tar.xz | |
Merge zizzer:/bk/newmem
into zeep.pool:/z/saidi/tmp/m5.newmem
--HG--
extra : convert_revision : f4fa62290ca2bbd4726fb6c8e89655dade53bb68
Diffstat (limited to 'src/python')
| -rw-r--r-- | src/python/m5/objects/PhysicalMemory.py | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/src/python/m5/objects/PhysicalMemory.py b/src/python/m5/objects/PhysicalMemory.py index 9cc7510a2..f4818763f 100644 --- a/src/python/m5/objects/PhysicalMemory.py +++ b/src/python/m5/objects/PhysicalMemory.py @@ -7,3 +7,21 @@ class PhysicalMemory(MemObject): range = Param.AddrRange("Device Address") file = Param.String('', "memory mapped file") latency = Param.Latency(Parent.clock, "latency of an access") + +class DRAMMemory(PhysicalMemory): + type = 'DRAMMemory' + # Many of these should be observed from the configuration + cpu_ratio = Param.Int(5,"ratio between CPU speed and memory bus speed") + mem_type = Param.String("SDRAM", "Type of DRAM (DRDRAM, SDRAM)") + mem_actpolicy = Param.String("open", "Open/Close policy") + memctrladdr_type = Param.String("interleaved", "Mapping interleaved or direct") + bus_width = Param.Int(16, "") + act_lat = Param.Int(2, "RAS to CAS delay") + cas_lat = Param.Int(1, "CAS delay") + war_lat = Param.Int(2, "write after read delay") + pre_lat = Param.Int(2, "precharge delay") + dpl_lat = Param.Int(2, "data in to precharge delay") + trc_lat = Param.Int(6, "row cycle delay") + num_banks = Param.Int(4, "Number of Banks") + num_cpus = Param.Int(4, "Number of CPUs connected to DRAM") + |