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| author | Ali Saidi <saidi@eecs.umich.edu> | 2007-02-13 15:58:06 -0500 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-02-13 15:58:06 -0500 |
| commit | e3dcbc94f77302b23365d191d43d60b1425c76b1 (patch) | |
| tree | f7bf5217596671ddd9dddb028c11084158117d46 /src/python | |
| parent | dc7ef3d489f3ae54383f4b7fd525f41d339c9895 (diff) | |
| download | gem5-e3dcbc94f77302b23365d191d43d60b1425c76b1.tar.xz | |
Make mulitple consoles work and be distinguishable from each other
src/dev/alpha/tsunamireg.h:
get rid of things that aren't really tsunami registers
src/dev/platform.hh:
src/dev/uart.cc:
the uart pointer isn't used anymore
src/dev/simconsole.cc:
make the simconsole print something more useful to distinguish between various consoles in a single system
src/dev/uart8250.hh:
put the needed uart defines in here rather than including them from tsunamireg
src/python/m5/objects/T1000.py:
add a console to the T1000 config for the hypervisor
--HG--
extra : convert_revision : 76ca92122e611eaf76b989bc699582eef8297be8
Diffstat (limited to 'src/python')
| -rw-r--r-- | src/python/m5/objects/T1000.py | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/python/m5/objects/T1000.py b/src/python/m5/objects/T1000.py index 85c4db6df..3ab6d4283 100644 --- a/src/python/m5/objects/T1000.py +++ b/src/python/m5/objects/T1000.py @@ -69,16 +69,19 @@ class T1000(Platform): fake_ssi = IsaFake(pio_addr=0xff00000000, pio_size=0x10000000) #warn_access="Accessing SSI -- Unimplemented!") + hconsole = SimConsole(listener = ConsoleListener()) hvuart = Uart8250(pio_addr=0xfff0c2c000) htod = DumbTOD() + pconsole = SimConsole(listener = ConsoleListener()) puart0 = Uart8250(pio_addr=0x1f10000000) - console = SimConsole(listener = ConsoleListener()) # Attach I/O devices to specified bus object. Can't do this # earlier, since the bus object itself is typically defined at the # System level. def attachIO(self, bus): + self.hvuart.sim_console = self.hconsole + self.puart0.sim_console = self.pconsole self.fake_clk.pio = bus.port self.fake_membnks.pio = bus.port self.fake_iob.pio = bus.port |