Merge ktlim@zizzer:/bk/newmem

into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge

configs/test/fs.py:
configs/test/test.py:
    SCCS merged

--HG--
extra : convert_revision : 7b2dbcd5881fac01dec38001c4131e73b5be52b5

4 files changed, 7 insertions, 5 deletions

diff --git a/src/python/m5/config.py b/src/python/m5/config.py
index e7fe7b78f..df4b74cbd 100644
--- a/src/python/m5/config.py
+++ b/src/python/m5/config.py
@@ -547,8 +547,7 @@ class SimObject(object):
         count = 0
         # ParamContexts don't serialize
         if isinstance(self, SimObject) and not isinstance(self, ParamContext):
-            if not self._ccObject.drain(drain_event):
-                count = 1
+            count += self._ccObject.drain(drain_event)
         if recursive:
             for child in self._children.itervalues():
                 count += child.startDrain(drain_event, True)
@@ -561,7 +560,7 @@ class SimObject(object):
             child.resume()
 
     def changeTiming(self, mode):
-        if isinstance(self, SimObject) and not isinstance(self, ParamContext):
+        if isinstance(self, System):
             self._ccObject.setMemoryMode(mode)
         for child in self._children.itervalues():
             child.changeTiming(mode)
diff --git a/src/python/m5/main.py b/src/python/m5/main.py
index c97390d25..a757aaf1a 100644
--- a/src/python/m5/main.py
+++ b/src/python/m5/main.py
@@ -182,7 +182,7 @@ options = attrdict()
 arguments = []
 
 def usage(exitcode=None):
-    print parser.help
+    parser.print_help()
     if exitcode is not None:
         sys.exit(exitcode)
 
diff --git a/src/python/m5/objects/BaseCPU.py b/src/python/m5/objects/BaseCPU.py
index 2e78578df..5bf98be9c 100644
--- a/src/python/m5/objects/BaseCPU.py
+++ b/src/python/m5/objects/BaseCPU.py
@@ -6,10 +6,10 @@ class BaseCPU(SimObject):
     abstract = True
     mem = Param.MemObject("memory")
 
+    system = Param.System(Parent.any, "system object")
     if build_env['FULL_SYSTEM']:
         dtb = Param.AlphaDTB("Data TLB")
         itb = Param.AlphaITB("Instruction TLB")
-        system = Param.System(Parent.any, "system object")
         cpu_id = Param.Int(-1, "CPU identifier")
     else:
         workload = VectorParam.Process("processes to run")
diff --git a/src/python/m5/objects/System.py b/src/python/m5/objects/System.py
index 9a1e1d690..386f39277 100644
--- a/src/python/m5/objects/System.py
+++ b/src/python/m5/objects/System.py
@@ -1,9 +1,12 @@
 from m5 import build_env
 from m5.config import *
 
+class MemoryMode(Enum): vals = ['invalid', 'atomic', 'timing']
+
 class System(SimObject):
     type = 'System'
     physmem = Param.PhysicalMemory(Parent.any, "phsyical memory")
+    mem_mode = Param.MemoryMode('atomic', "The mode the memory system is in")
     if build_env['FULL_SYSTEM']:
         boot_cpu_frequency = Param.Frequency(Self.cpu[0].clock.frequency,
                                              "boot processor frequency")