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author | Steve Reinhardt <stever@eecs.umich.edu> | 2006-08-18 00:17:21 -0400 |
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committer | Steve Reinhardt <stever@eecs.umich.edu> | 2006-08-18 00:17:21 -0400 |
commit | a12dbc3074d505789aeeacd312e3a708d7a1f03c (patch) | |
tree | fe9f450951467e854f3596929b18f35c3eef4d29 /src/python | |
parent | 4e3164617ad709cb6d4b0f8fbbdfd596f4d6f236 (diff) | |
download | gem5-a12dbc3074d505789aeeacd312e3a708d7a1f03c.tar.xz |
Update reference outputs
--HG--
extra : convert_revision : 110a6c51cc1c562d115492b7360bfdbbded8eefd
Diffstat (limited to 'src/python')
-rw-r--r-- | src/python/m5/objects/BaseCPU.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/python/m5/objects/BaseCPU.py b/src/python/m5/objects/BaseCPU.py index 01458aeb4..81e09c94c 100644 --- a/src/python/m5/objects/BaseCPU.py +++ b/src/python/m5/objects/BaseCPU.py @@ -6,7 +6,7 @@ from Bus import Bus class BaseCPU(SimObject): type = 'BaseCPU' abstract = True - mem = Param.PhysicalMemory(Parent.any, "memory") + mem = Param.MemObject("memory") system = Param.System(Parent.any, "system object") if build_env['FULL_SYSTEM']: |