Merge zizzer:/bk/newmem

into zeep.pool:/z/saidi/work/m5.newmem.head --HG-- extra : convert_revision : 8c747208d72ffbb0160a2ad4a75383420debdf83
author: Ali Saidi <saidi@eecs.umich.edu> 2006-07-19 17:59:04 -0400
committer: Ali Saidi <saidi@eecs.umich.edu> 2006-07-19 17:59:04 -0400
commit: 15e5ce96c76a20b9b27e5f7d7ed29e962422ad1a (patch)
tree: 610a888b2de5d25c166f65819d8ad3058d13723c /src/python
parent: b36796914af8bfc6729cc8a519e57572460e43e8 (diff)
parent: 6175f712b3216f3e5387b07d9c41c1931c09acd9 (diff)
download: gem5-15e5ce96c76a20b9b27e5f7d7ed29e962422ad1a.tar.xz
17 files changed, 611 insertions, 156 deletions
diff --git a/src/python/SConscript b/src/python/SConscript
index 3a9def9a8..c9e713199 100644
--- a/src/python/SConscript
+++ b/src/python/SConscript
@@ -75,16 +75,27 @@ def addPkg(pkgdir):
 # build_env flags.
 def MakeDefinesPyFile(target, source, env):
     f = file(str(target[0]), 'w')
-    print >>f, "m5_build_env = ",
-    print >>f, source[0]
+    print >>f, "m5_build_env = ", source[0]
     f.close()
 
 optionDict = dict([(opt, env[opt]) for opt in env.ExportOptions])
 env.Command('m5/defines.py', Value(optionDict), MakeDefinesPyFile)
 
+def MakeInfoPyFile(target, source, env):
+    f = file(str(target[0]), 'w')
+    for src in source:
+        data = ''.join(file(src.srcnode().abspath, 'r').xreadlines())
+        print >>f, "%s = %s" % (src, repr(data))
+    f.close()
+
+env.Command('m5/info.py',
+            [ '#/AUTHORS', '#/LICENSE', '#/README', '#/RELEASE_NOTES' ],
+            MakeInfoPyFile)
+
 # Now specify the packages & files for the zip archive.
 addPkg('m5')
 pyzip_files.append('m5/defines.py')
+pyzip_files.append('m5/info.py')
 pyzip_files.append(join(env['ROOT'], 'util/pbs/jobfile.py'))
 
 env.Command(['swig/cc_main_wrap.cc', 'm5/cc_main.py'],
diff --git a/src/python/m5/__init__.py b/src/python/m5/__init__.py
index 828165d15..3d0e3defa 100644
--- a/src/python/m5/__init__.py
+++ b/src/python/m5/__init__.py
@@ -27,14 +27,14 @@
 # Authors: Nathan Binkert
 #          Steve Reinhardt
 
-import sys, os, time, atexit, optparse
+import atexit, os, sys
 
 # import the SWIG-wrapped main C++ functions
 import cc_main
 # import a few SWIG-wrapped items (those that are likely to be used
 # directly by user scripts) completely into this module for
 # convenience
-from cc_main import simulate, SimLoopExitEvent, setCheckpointDir
+from cc_main import simulate, SimLoopExitEvent
 
 # import the m5 compile options
 import defines
@@ -57,111 +57,6 @@ def AddToPath(path):
     # so place the new dir right after that.
     sys.path.insert(1, path)
 
-
-# The m5 module's pointer to the parsed options object
-options = None
-
-
-# User should call this function after calling parse_args() to pass
-# parsed standard option values back into the m5 module for
-# processing.
-def setStandardOptions(_options):
-    # Set module global var
-    global options
-    options = _options
-    # tell C++ about output directory
-    cc_main.setOutputDir(options.outdir)
-
-# Callback to set trace flags.  Not necessarily the best way to do
-# things in the long run (particularly if we change how these global
-# options are handled).
-def setTraceFlags(option, opt_str, value, parser):
-    objects.Trace.flags = value
-
-def setTraceStart(option, opt_str, value, parser):
-    objects.Trace.start = value
-
-def setTraceFile(option, opt_str, value, parser):
-    objects.Trace.file = value
-
-def noPCSymbol(option, opt_str, value, parser):
-    objects.ExecutionTrace.pc_symbol = False
-
-def noPrintCycle(option, opt_str, value, parser):
-    objects.ExecutionTrace.print_cycle = False
-
-def noPrintOpclass(option, opt_str, value, parser):
-    objects.ExecutionTrace.print_opclass = False
-
-def noPrintThread(option, opt_str, value, parser):
-    objects.ExecutionTrace.print_thread = False
-
-def noPrintEA(option, opt_str, value, parser):
-    objects.ExecutionTrace.print_effaddr = False
-
-def noPrintData(option, opt_str, value, parser):
-    objects.ExecutionTrace.print_data = False
-
-def printFetchseq(option, opt_str, value, parser):
-    objects.ExecutionTrace.print_fetchseq = True
-
-def printCpseq(option, opt_str, value, parser):
-    objects.ExecutionTrace.print_cpseq = True
-
-def dumpOnExit(option, opt_str, value, parser):
-    objects.Trace.dump_on_exit = True
-
-def debugBreak(option, opt_str, value, parser):
-    objects.Debug.break_cycles = value
-
-def statsTextFile(option, opt_str, value, parser):
-    objects.Statistics.text_file = value
-
-# Standard optparse options.  Need to be explicitly included by the
-# user script when it calls optparse.OptionParser().
-standardOptions = [
-    optparse.make_option("--outdir", type="string", default="."),
-    optparse.make_option("--traceflags", type="string", action="callback",
-                         callback=setTraceFlags),
-    optparse.make_option("--tracestart", type="int", action="callback",
-                         callback=setTraceStart),
-    optparse.make_option("--tracefile", type="string", action="callback",
-                         callback=setTraceFile),
-    optparse.make_option("--nopcsymbol",
-                         action="callback", callback=noPCSymbol,
-                         help="Disable PC symbols in trace output"),
-    optparse.make_option("--noprintcycle",
-                         action="callback", callback=noPrintCycle,
-                         help="Don't print cycle numbers in trace output"),
-    optparse.make_option("--noprintopclass",
-                         action="callback", callback=noPrintOpclass,
-                         help="Don't print op class type in trace output"),
-    optparse.make_option("--noprintthread",
-                         action="callback", callback=noPrintThread,
-                         help="Don't print thread number in trace output"),
-    optparse.make_option("--noprinteffaddr",
-                         action="callback", callback=noPrintEA,
-                         help="Don't print effective address in trace output"),
-    optparse.make_option("--noprintdata",
-                         action="callback", callback=noPrintData,
-                         help="Don't print result data in trace output"),
-    optparse.make_option("--printfetchseq",
-                         action="callback", callback=printFetchseq,
-                         help="Print fetch sequence numbers in trace output"),
-    optparse.make_option("--printcpseq",
-                         action="callback", callback=printCpseq,
-                         help="Print correct path sequence numbers in trace output"),
-    optparse.make_option("--dumponexit",
-                         action="callback", callback=dumpOnExit,
-                         help="Dump trace buffer on exit"),
-    optparse.make_option("--debugbreak", type="int", metavar="CYCLE",
-                         action="callback", callback=debugBreak,
-                         help="Cycle to create a breakpoint"),
-    optparse.make_option("--statsfile", type="string", action="callback",
-                         callback=statsTextFile, metavar="FILE",
-                         help="Sets the output file for the statistics")
-    ]
-
 # make a SmartDict out of the build options for our local use
 import smartdict
 build_env = smartdict.SmartDict()
@@ -171,12 +66,13 @@ build_env.update(defines.m5_build_env)
 env = smartdict.SmartDict()
 env.update(os.environ)
 
-
 # Function to provide to C++ so it can look up instances based on paths
 def resolveSimObject(name):
     obj = config.instanceDict[name]
     return obj.getCCObject()
 
+from main import options, arguments, main
+
 # The final hook to generate .ini files.  Called from the user script
 # once the config is built.
 def instantiate(root):
@@ -213,35 +109,50 @@ atexit.register(cc_main.doExitCleanup)
 # matter since most scripts will probably 'from m5.objects import *'.
 import objects
 
-def doQuiesce(root):
-    quiesce = cc_main.createCountedQuiesce()
-    unready_objects = root.startQuiesce(quiesce, True)
-    # If we've got some objects that can't quiesce immediately, then simulate
+# This loops until all objects have been fully drained.
+def doDrain(root):
+    all_drained = drain(root)
+    while (not all_drained):
+        all_drained = drain(root)
+
+# Tries to drain all objects.  Draining might not be completed unless
+# all objects return that they are drained on the first call.  This is
+# because as objects drain they may cause other objects to no longer
+# be drained.
+def drain(root):
+    all_drained = False
+    drain_event = cc_main.createCountedDrain()
+    unready_objects = root.startDrain(drain_event, True)
+    # If we've got some objects that can't drain immediately, then simulate
     if unready_objects > 0:
-        quiesce.setCount(unready_objects)
+        drain_event.setCount(unready_objects)
         simulate()
-    cc_main.cleanupCountedQuiesce(quiesce)
+    else:
+        all_drained = True
+    cc_main.cleanupCountedDrain(drain_event)
+    return all_drained
 
 def resume(root):
     root.resume()
 
-def checkpoint(root):
+def checkpoint(root, dir):
     if not isinstance(root, objects.Root):
         raise TypeError, "Object is not a root object. Checkpoint must be called on a root object."
-    doQuiesce(root)
+    doDrain(root)
     print "Writing checkpoint"
-    cc_main.serializeAll()
+    cc_main.serializeAll(dir)
     resume(root)
 
-def restoreCheckpoint(root):
+def restoreCheckpoint(root, dir):
     print "Restoring from checkpoint"
-    cc_main.unserializeAll()
+    cc_main.unserializeAll(dir)
+    resume(root)
 
 def changeToAtomic(system):
     if not isinstance(system, objects.Root) and not isinstance(system, System):
         raise TypeError, "Object is not a root or system object.  Checkpoint must be "
         "called on a root object."
-    doQuiesce(system)
+    doDrain(system)
     print "Changing memory mode to atomic"
     system.changeTiming(cc_main.SimObject.Atomic)
     resume(system)
@@ -250,7 +161,7 @@ def changeToTiming(system):
     if not isinstance(system, objects.Root) and not isinstance(system, System):
         raise TypeError, "Object is not a root or system object.  Checkpoint must be "
         "called on a root object."
-    doQuiesce(system)
+    doDrain(system)
     print "Changing memory mode to timing"
     system.changeTiming(cc_main.SimObject.Timing)
     resume(system)
@@ -271,16 +182,16 @@ def switchCpus(cpuList):
         if not isinstance(cpu, objects.BaseCPU):
             raise TypeError, "%s is not of type BaseCPU", cpu
 
-    # Quiesce all of the individual CPUs
-    quiesce = cc_main.createCountedQuiesce()
+    # Drain all of the individual CPUs
+    drain_event = cc_main.createCountedDrain()
     unready_cpus = 0
     for old_cpu in old_cpus:
-        unready_cpus += old_cpu.startQuiesce(quiesce, False)
-    # If we've got some objects that can't quiesce immediately, then simulate
+        unready_cpus += old_cpu.startDrain(drain_event, False)
+    # If we've got some objects that can't drain immediately, then simulate
     if unready_cpus > 0:
-        quiesce.setCount(unready_cpus)
+        drain_event.setCount(unready_cpus)
         simulate()
-    cc_main.cleanupCountedQuiesce(quiesce)
+    cc_main.cleanupCountedDrain(drain_event)
     # Now all of the CPUs are ready to be switched out
     for old_cpu in old_cpus:
         old_cpu._ccObject.switchOut()
diff --git a/src/python/m5/attrdict.py b/src/python/m5/attrdict.py
new file mode 100644
index 000000000..4ee7f1b8c
--- /dev/null
+++ b/src/python/m5/attrdict.py
@@ -0,0 +1,61 @@
+# Copyright (c) 2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+
+__all__ = [ 'attrdict' ]
+
+class attrdict(dict):
+    def __getattr__(self, attr):
+        if attr in self:
+            return self.__getitem__(attr)
+        return super(attrdict, self).__getattribute__(attr)
+
+    def __setattr__(self, attr, value):
+        if attr in dir(self):
+            return super(attrdict, self).__setattr__(attr, value)
+        return self.__setitem__(attr, value)
+
+    def __delattr__(self, attr):
+        if attr in self:
+            return self.__delitem__(attr)
+        return super(attrdict, self).__delattr__(attr, value)
+
+if __name__ == '__main__':
+    x = attrdict()
+    x.y = 1
+    x['z'] = 2
+    print x['y'], x.y
+    print x['z'], x.z
+    print dir(x)
+    print x
+
+    print
+
+    del x['y']
+    del x.z
+    print dir(x)
+    print(x)
diff --git a/src/python/m5/config.py b/src/python/m5/config.py
index 6f2873d40..df4b74cbd 100644
--- a/src/python/m5/config.py
+++ b/src/python/m5/config.py
@@ -543,15 +543,14 @@ class SimObject(object):
         for child in self._children.itervalues():
             child.connectPorts()
 
-    def startQuiesce(self, quiesce_event, recursive):
+    def startDrain(self, drain_event, recursive):
         count = 0
         # ParamContexts don't serialize
         if isinstance(self, SimObject) and not isinstance(self, ParamContext):
-            if self._ccObject.quiesce(quiesce_event):
-                count = 1
+            count += self._ccObject.drain(drain_event)
         if recursive:
             for child in self._children.itervalues():
-                count += child.startQuiesce(quiesce_event, True)
+                count += child.startDrain(drain_event, True)
         return count
 
     def resume(self):
@@ -561,7 +560,7 @@ class SimObject(object):
             child.resume()
 
     def changeTiming(self, mode):
-        if isinstance(self, SimObject) and not isinstance(self, ParamContext):
+        if isinstance(self, System):
             self._ccObject.setMemoryMode(mode)
         for child in self._children.itervalues():
             child.changeTiming(mode)
@@ -666,7 +665,8 @@ class BaseProxy(object):
                 result, done = self.find(obj)
 
         if not done:
-            raise AttributeError, "Can't resolve proxy '%s' from '%s'" % \
+            raise AttributeError, \
+                  "Can't resolve proxy '%s' from '%s'" % \
                   (self.path(), base.path())
 
         if isinstance(result, BaseProxy):
diff --git a/src/python/m5/main.py b/src/python/m5/main.py
new file mode 100644
index 000000000..a757aaf1a
--- /dev/null
+++ b/src/python/m5/main.py
@@ -0,0 +1,323 @@
+# Copyright (c) 2005 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+
+import code, optparse, os, socket, sys
+from datetime import datetime
+from attrdict import attrdict
+
+try:
+    import info
+except ImportError:
+    info = None
+
+__all__ = [ 'options', 'arguments', 'main' ]
+
+usage="%prog [m5 options] script.py [script options]"
+version="%prog 2.0"
+brief_copyright='''
+Copyright (c) 2001-2006
+The Regents of The University of Michigan
+All Rights Reserved
+'''
+
+# there's only one option parsing done, so make it global and add some
+# helper functions to make it work well.
+parser = optparse.OptionParser(usage=usage, version=version,
+                               description=brief_copyright,
+                               formatter=optparse.TitledHelpFormatter())
+parser.disable_interspersed_args()
+
+# current option group
+group = None
+
+def set_group(*args, **kwargs):
+    '''set the current option group'''
+    global group
+    if not args and not kwargs:
+        group = None
+    else:
+        group = parser.add_option_group(*args, **kwargs)
+
+class splitter(object):
+    def __init__(self, split):
+        self.split = split
+    def __call__(self, option, opt_str, value, parser):
+        getattr(parser.values, option.dest).extend(value.split(self.split))
+
+def add_option(*args, **kwargs):
+    '''add an option to the current option group, or global none set'''
+
+    # if action=split, but allows the option arguments
+    # themselves to be lists separated by the split variable'''
+
+    if kwargs.get('action', None) == 'append' and 'split' in kwargs:
+        split = kwargs.pop('split')
+        kwargs['default'] = []
+        kwargs['type'] = 'string'
+        kwargs['action'] = 'callback'
+        kwargs['callback'] = splitter(split)
+
+    if group:
+        return group.add_option(*args, **kwargs)
+
+    return parser.add_option(*args, **kwargs)
+
+def bool_option(name, default, help):
+    '''add a boolean option called --name and --no-name.
+    Display help depending on which is the default'''
+
+    tname = '--%s' % name
+    fname = '--no-%s' % name
+    dest = name.replace('-', '_')
+    if default:
+        thelp = optparse.SUPPRESS_HELP
+        fhelp = help
+    else:
+        thelp = help
+        fhelp = optparse.SUPPRESS_HELP
+
+    add_option(tname, action="store_true", default=default, help=thelp)
+    add_option(fname, action="store_false", dest=dest, help=fhelp)
+
+# Help options
+add_option('-A', "--authors", action="store_true", default=False,
+    help="Show author information")
+add_option('-C', "--copyright", action="store_true", default=False,
+    help="Show full copyright information")
+add_option('-R', "--readme", action="store_true", default=False,
+    help="Show the readme")
+add_option('-N', "--release-notes", action="store_true", default=False,
+    help="Show the release notes")
+
+# Options for configuring the base simulator
+add_option('-d', "--outdir", metavar="DIR", default=".",
+    help="Set the output directory to DIR [Default: %default]")
+add_option('-i', "--interactive", action="store_true", default=False,
+    help="Invoke the interactive interpreter after running the script")
+add_option("--pdb", action="store_true", default=False,
+    help="Invoke the python debugger before running the script")
+add_option('-p', "--path", metavar="PATH[:PATH]", action='append', split=':',
+    help="Prepend PATH to the system path when invoking the script")
+add_option('-q', "--quiet", action="count", default=0,
+    help="Reduce verbosity")
+add_option('-v', "--verbose", action="count", default=0,
+    help="Increase verbosity")
+
+# Statistics options
+set_group("Statistics Options")
+add_option("--stats-file", metavar="FILE", default="m5stats.txt",
+    help="Sets the output file for statistics [Default: %default]")
+
+# Debugging options
+set_group("Debugging Options")
+add_option("--debug-break", metavar="TIME[,TIME]", action='append', split=',',
+    help="Cycle to create a breakpoint")
+
+# Tracing options
+set_group("Trace Options")
+add_option("--trace-flags", metavar="FLAG[,FLAG]", action='append', split=',',
+    help="Sets the flags for tracing")
+add_option("--trace-start", metavar="TIME", default='0s',
+    help="Start tracing at TIME (must have units)")
+add_option("--trace-file", metavar="FILE", default="cout",
+    help="Sets the output file for tracing [Default: %default]")
+add_option("--trace-circlebuf", metavar="SIZE", type="int", default=0,
+    help="If SIZE is non-zero, turn on the circular buffer with SIZE lines")
+add_option("--no-trace-circlebuf", action="store_const", const=0,
+    dest='trace_circlebuf', help=optparse.SUPPRESS_HELP)
+bool_option("trace-dumponexit", default=False,
+    help="Dump trace buffer on exit")
+add_option("--trace-ignore", metavar="EXPR", action='append', split=':',
+    help="Ignore EXPR sim objects")
+
+# Execution Trace options
+set_group("Execution Trace Options")
+bool_option("speculative", default=True,
+    help="Don't capture speculative instructions")
+bool_option("print-cycle", default=True,
+    help="Don't print cycle numbers in trace output")
+bool_option("print-symbol", default=True,
+    help="Disable PC symbols in trace output")
+bool_option("print-opclass", default=True,
+    help="Don't print op class type in trace output")
+bool_option("print-thread", default=True,
+    help="Don't print thread number in trace output")
+bool_option("print-effaddr", default=True,
+    help="Don't print effective address in trace output")
+bool_option("print-data", default=True,
+    help="Don't print result data in trace output")
+bool_option("print-iregs", default=False,
+    help="Print fetch sequence numbers in trace output")
+bool_option("print-fetch-seq", default=False,
+    help="Print fetch sequence numbers in trace output")
+bool_option("print-cpseq", default=False,
+    help="Print correct path sequence numbers in trace output")
+
+options = attrdict()
+arguments = []
+
+def usage(exitcode=None):
+    parser.print_help()
+    if exitcode is not None:
+        sys.exit(exitcode)
+
+def parse_args():
+    _opts,args = parser.parse_args()
+    opts = attrdict(_opts.__dict__)
+
+    # setting verbose and quiet at the same time doesn't make sense
+    if opts.verbose > 0 and opts.quiet > 0:
+        usage(2)
+
+    # store the verbosity in a single variable.  0 is default,
+    # negative numbers represent quiet and positive values indicate verbose
+    opts.verbose -= opts.quiet
+
+    del opts.quiet
+
+    options.update(opts)
+    arguments.extend(args)
+    return opts,args
+
+def main():
+    import cc_main
+
+    parse_args()
+
+    done = False
+    if options.copyright:
+        done = True
+        print info.LICENSE
+        print
+
+    if options.authors:
+        done = True
+        print 'Author information:'
+        print
+        print info.AUTHORS
+        print
+
+    if options.readme:
+        done = True
+        print 'Readme:'
+        print
+        print info.README
+        print
+
+    if options.release_notes:
+        done = True
+        print 'Release Notes:'
+        print
+        print info.RELEASE_NOTES
+        print
+
+    if done:
+        sys.exit(0)
+
+    if options.verbose >= 0:
+        print "M5 Simulator System"
+        print brief_copyright
+        print
+        print "M5 compiled %s" % cc_main.cvar.compileDate;
+        print "M5 started %s" % datetime.now().ctime()
+        print "M5 executing on %s" % socket.gethostname()
+
+    # check to make sure we can find the listed script
+    if not arguments or not os.path.isfile(arguments[0]):
+        if arguments and not os.path.isfile(arguments[0]):
+            print "Script %s not found" % arguments[0]
+        usage(2)
+
+    # tell C++ about output directory
+    cc_main.setOutputDir(options.outdir)
+
+    # update the system path with elements from the -p option
+    sys.path[0:0] = options.path
+
+    import objects
+
+    # set stats options
+    objects.Statistics.text_file = options.stats_file
+
+    # set debugging options
+    objects.Debug.break_cycles = options.debug_break
+
+    # set tracing options
+    objects.Trace.flags = options.trace_flags
+    objects.Trace.start = options.trace_start
+    objects.Trace.file = options.trace_file
+    objects.Trace.bufsize = options.trace_circlebuf
+    objects.Trace.dump_on_exit = options.trace_dumponexit
+    objects.Trace.ignore = options.trace_ignore
+
+    # set execution trace options
+    objects.ExecutionTrace.speculative = options.speculative
+    objects.ExecutionTrace.print_cycle = options.print_cycle
+    objects.ExecutionTrace.pc_symbol = options.print_symbol
+    objects.ExecutionTrace.print_opclass = options.print_opclass
+    objects.ExecutionTrace.print_thread = options.print_thread
+    objects.ExecutionTrace.print_effaddr = options.print_effaddr
+    objects.ExecutionTrace.print_data = options.print_data
+    objects.ExecutionTrace.print_iregs = options.print_iregs
+    objects.ExecutionTrace.print_fetchseq = options.print_fetch_seq
+    objects.ExecutionTrace.print_cpseq = options.print_cpseq
+
+    sys.argv = arguments
+    sys.path = [ os.path.dirname(sys.argv[0]) ] + sys.path
+
+    scope = { '__file__' : sys.argv[0] }
+
+    # we want readline if we're doing anything interactive
+    if options.interactive or options.pdb:
+        exec("import readline", scope)
+
+    # if pdb was requested, execfile the thing under pdb, otherwise,
+    # just do the execfile normally
+    if options.pdb:
+        from pdb import Pdb
+        debugger = Pdb()
+        debugger.run('execfile("%s")' % sys.argv[0], scope)
+    else:
+        execfile(sys.argv[0], scope)
+
+    # once the script is done
+    if options.interactive:
+        interact = code.InteractiveConsole(scope)
+        interact.interact("M5 Interactive Console")
+
+if __name__ == '__main__':
+    from pprint import pprint
+
+    parse_args()
+
+    print 'opts:'
+    pprint(options, indent=4)
+    print
+
+    print 'args:'
+    pprint(arguments, indent=4)
diff --git a/src/python/m5/objects/BaseCPU.py b/src/python/m5/objects/BaseCPU.py
index 2e78578df..5bf98be9c 100644
--- a/src/python/m5/objects/BaseCPU.py
+++ b/src/python/m5/objects/BaseCPU.py
@@ -6,10 +6,10 @@ class BaseCPU(SimObject):
     abstract = True
     mem = Param.MemObject("memory")
 
+    system = Param.System(Parent.any, "system object")
     if build_env['FULL_SYSTEM']:
         dtb = Param.AlphaDTB("Data TLB")
         itb = Param.AlphaITB("Instruction TLB")
-        system = Param.System(Parent.any, "system object")
         cpu_id = Param.Int(-1, "CPU identifier")
     else:
         workload = VectorParam.Process("processes to run")
diff --git a/src/python/m5/objects/Bus.py b/src/python/m5/objects/Bus.py
index 019e15034..e0278e6c3 100644
--- a/src/python/m5/objects/Bus.py
+++ b/src/python/m5/objects/Bus.py
@@ -4,4 +4,5 @@ from MemObject import MemObject
 class Bus(MemObject):
     type = 'Bus'
     port = VectorPort("vector port for connecting devices")
+    default = Port("Default port for requests that aren't handeled by a device.")
     bus_id = Param.Int(0, "blah")
diff --git a/src/python/m5/objects/Device.py b/src/python/m5/objects/Device.py
index 222f750da..f72c8e73f 100644
--- a/src/python/m5/objects/Device.py
+++ b/src/python/m5/objects/Device.py
@@ -12,7 +12,7 @@ class BasicPioDevice(PioDevice):
     type = 'BasicPioDevice'
     abstract = True
     pio_addr = Param.Addr("Device Address")
-    pio_latency = Param.Tick(1, "Programmed IO latency in simticks")
+    pio_latency = Param.Latency('1ns', "Programmed IO latency in simticks")
 
 class DmaDevice(PioDevice):
     type = 'DmaDevice'
diff --git a/src/python/m5/objects/DiskImage.py b/src/python/m5/objects/DiskImage.py
index 70d8b2e45..a98b35a4f 100644
--- a/src/python/m5/objects/DiskImage.py
+++ b/src/python/m5/objects/DiskImage.py
@@ -10,6 +10,6 @@ class RawDiskImage(DiskImage):
 
 class CowDiskImage(DiskImage):
     type = 'CowDiskImage'
-    child = Param.DiskImage("child image")
+    child = Param.DiskImage(RawDiskImage(read_only=True),
+                            "child image")
     table_size = Param.Int(65536, "initial table size")
-    image_file = ''
diff --git a/src/python/m5/objects/Ethernet.py b/src/python/m5/objects/Ethernet.py
index 418670592..db7efe004 100644
--- a/src/python/m5/objects/Ethernet.py
+++ b/src/python/m5/objects/Ethernet.py
@@ -1,7 +1,7 @@
 from m5 import build_env
 from m5.config import *
 from Device import DmaDevice
-from Pci import PciDevice
+from Pci import PciDevice, PciConfigData
 
 class EtherInt(SimObject):
     type = 'EtherInt'
@@ -84,6 +84,26 @@ class EtherDevBase(PciDevice):
     tx_thread = Param.Bool(False, "dedicated kernel threads for receive")
     rss = Param.Bool(False, "Receive Side Scaling")
 
+class NSGigEPciData(PciConfigData):
+    VendorID = 0x100B
+    DeviceID = 0x0022
+    Status = 0x0290
+    SubClassCode = 0x00
+    ClassCode = 0x02
+    ProgIF = 0x00
+    BAR0 = 0x00000001
+    BAR1 = 0x00000000
+    BAR2 = 0x00000000
+    BAR3 = 0x00000000
+    BAR4 = 0x00000000
+    BAR5 = 0x00000000
+    MaximumLatency = 0x34
+    MinimumGrant = 0xb0
+    InterruptLine = 0x1e
+    InterruptPin = 0x01
+    BAR0Size = '256B'
+    BAR1Size = '4kB'
+
 class NSGigE(EtherDevBase):
     type = 'NSGigE'
 
@@ -91,11 +111,32 @@ class NSGigE(EtherDevBase):
     dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
     dma_no_allocate = Param.Bool(True, "Should we allocate cache on read")
 
+    configdata = NSGigEPciData()
+
 
 class NSGigEInt(EtherInt):
     type = 'NSGigEInt'
     device = Param.NSGigE("Ethernet device of this interface")
 
+class SinicPciData(PciConfigData):
+    VendorID = 0x1291
+    DeviceID = 0x1293
+    Status = 0x0290
+    SubClassCode = 0x00
+    ClassCode = 0x02
+    ProgIF = 0x00
+    BAR0 = 0x00000000
+    BAR1 = 0x00000000
+    BAR2 = 0x00000000
+    BAR3 = 0x00000000
+    BAR4 = 0x00000000
+    BAR5 = 0x00000000
+    MaximumLatency = 0x34
+    MinimumGrant = 0xb0
+    InterruptLine = 0x1e
+    InterruptPin = 0x01
+    BAR0Size = '64kB'
+
 class Sinic(EtherDevBase):
     type = 'Sinic'
 
@@ -111,6 +152,8 @@ class Sinic(EtherDevBase):
     delay_copy = Param.Bool(False, "Delayed copy transmit")
     virtual_addr = Param.Bool(False, "Virtual addressing")
 
+    configdata = SinicPciData()
+
 class SinicInt(EtherInt):
     type = 'SinicInt'
     device = Param.Sinic("Ethernet device of this interface")
diff --git a/src/python/m5/objects/Ide.py b/src/python/m5/objects/Ide.py
index 9ee578177..a5fe1b595 100644
--- a/src/python/m5/objects/Ide.py
+++ b/src/python/m5/objects/Ide.py
@@ -1,8 +1,31 @@
 from m5.config import *
-from Pci import PciDevice
+from Pci import PciDevice, PciConfigData
 
 class IdeID(Enum): vals = ['master', 'slave']
 
+class IdeControllerPciData(PciConfigData):
+    VendorID = 0x8086
+    DeviceID = 0x7111
+    Command = 0x0
+    Status = 0x280
+    Revision = 0x0
+    ClassCode = 0x01
+    SubClassCode = 0x01
+    ProgIF = 0x85
+    BAR0 = 0x00000001
+    BAR1 = 0x00000001
+    BAR2 = 0x00000001
+    BAR3 = 0x00000001
+    BAR4 = 0x00000001
+    BAR5 = 0x00000001
+    InterruptLine = 0x1f
+    InterruptPin = 0x01
+    BAR0Size = '8B'
+    BAR1Size = '4B'
+    BAR2Size = '8B'
+    BAR3Size = '4B'
+    BAR4Size = '16B'
+
 class IdeDisk(SimObject):
     type = 'IdeDisk'
     delay = Param.Latency('1us', "Fixed disk delay in microseconds")
@@ -12,3 +35,5 @@ class IdeDisk(SimObject):
 class IdeController(PciDevice):
     type = 'IdeController'
     disks = VectorParam.IdeDisk("IDE disks attached to this controller")
+
+    configdata =IdeControllerPciData()
diff --git a/src/python/m5/objects/O3CPU.py b/src/python/m5/objects/O3CPU.py
index 4ecfa8fbd..d6bc454ad 100644
--- a/src/python/m5/objects/O3CPU.py
+++ b/src/python/m5/objects/O3CPU.py
@@ -10,6 +10,8 @@ class DerivO3CPU(BaseCPU):
     checker = Param.BaseCPU(NULL, "checker")
 
     cachePorts = Param.Unsigned("Cache Ports")
+    icache_port = Port("Instruction Port")
+    dcache_port = Port("Data Port")
 
     decodeToFetchDelay = Param.Unsigned("Decode to fetch delay")
     renameToFetchDelay = Param.Unsigned("Rename to fetch delay")
@@ -37,12 +39,10 @@ class DerivO3CPU(BaseCPU):
                "Issue/Execute/Writeback delay")
     issueToExecuteDelay = Param.Unsigned("Issue to execute delay (internal "
               "to the IEW stage)")
+    dispatchWidth = Param.Unsigned("Dispatch width")
     issueWidth = Param.Unsigned("Issue width")
-    executeWidth = Param.Unsigned("Execute width")
-    executeIntWidth = Param.Unsigned("Integer execute width")
-    executeFloatWidth = Param.Unsigned("Floating point execute width")
-    executeBranchWidth = Param.Unsigned("Branch execute width")
-    executeMemoryWidth = Param.Unsigned("Memory execute width")
+    wbWidth = Param.Unsigned("Writeback width")
+    wbDepth = Param.Unsigned("Writeback depth")
     fuPool = Param.FUPool(NULL, "Functional Unit pool")
 
     iewToCommitDelay = Param.Unsigned("Issue/Execute/Writeback to commit "
@@ -53,6 +53,9 @@ class DerivO3CPU(BaseCPU):
     trapLatency = Param.Tick("Trap latency")
     fetchTrapLatency = Param.Tick("Fetch trap latency")
 
+    backComSize = Param.Unsigned("Time buffer size for backwards communication")
+    forwardComSize = Param.Unsigned("Time buffer size for forward communication")
+
     predType = Param.String("Branch predictor type ('local', 'tournament')")
     localPredictorSize = Param.Unsigned("Size of local predictor")
     localCtrBits = Param.Unsigned("Bits per counter")
diff --git a/src/python/m5/objects/OzoneCPU.py b/src/python/m5/objects/OzoneCPU.py
index 8aff89203..88fb63c74 100644
--- a/src/python/m5/objects/OzoneCPU.py
+++ b/src/python/m5/objects/OzoneCPU.py
@@ -9,6 +9,9 @@ class DerivOzoneCPU(BaseCPU):
 
     checker = Param.BaseCPU("Checker CPU")
 
+    icache_port = Port("Instruction Port")
+    dcache_port = Port("Data Port")
+
     width = Param.Unsigned("Width")
     frontEndWidth = Param.Unsigned("Front end width")
     backEndWidth = Param.Unsigned("Back end width")
diff --git a/src/python/m5/objects/Pci.py b/src/python/m5/objects/Pci.py
index 9e1e91b13..cc0d1cf4a 100644
--- a/src/python/m5/objects/Pci.py
+++ b/src/python/m5/objects/Pci.py
@@ -1,5 +1,5 @@
 from m5.config import *
-from Device import BasicPioDevice, DmaDevice
+from Device import BasicPioDevice, DmaDevice, PioDevice
 
 class PciConfigData(SimObject):
     type = 'PciConfigData'
@@ -38,18 +38,22 @@ class PciConfigData(SimObject):
     MaximumLatency = Param.UInt8(0x00, "Maximum Latency")
     MinimumGrant = Param.UInt8(0x00, "Minimum Grant")
 
-class PciConfigAll(BasicPioDevice):
+class PciConfigAll(PioDevice):
     type = 'PciConfigAll'
+    pio_latency = Param.Tick(1, "Programmed IO latency in simticks")
+    bus = Param.UInt8(0x00, "PCI bus to act as config space for")
+    size = Param.MemorySize32('16MB', "Size of config space")
+
 
 class PciDevice(DmaDevice):
     type = 'PciDevice'
     abstract = True
+    config = Port("PCI configuration space port")
     pci_bus = Param.Int("PCI bus")
     pci_dev = Param.Int("PCI device number")
     pci_func = Param.Int("PCI function code")
-    pio_latency = Param.Tick(1, "Programmed IO latency in simticks")
+    pio_latency = Param.Latency('1ns', "Programmed IO latency in simticks")
     configdata = Param.PciConfigData(Parent.any, "PCI Config data")
-    configspace = Param.PciConfigAll(Parent.any, "PCI Configspace")
 
 class PciFake(PciDevice):
     type = 'PciFake'
diff --git a/src/python/m5/objects/Root.py b/src/python/m5/objects/Root.py
index 373475a7a..33dd22620 100644
--- a/src/python/m5/objects/Root.py
+++ b/src/python/m5/objects/Root.py
@@ -7,7 +7,7 @@ from Debug import Debug
 
 class Root(SimObject):
     type = 'Root'
-    clock = Param.RootClock('200MHz', "tick frequency")
+    clock = Param.RootClock('1THz', "tick frequency")
     max_tick = Param.Tick('0', "maximum simulation ticks (0 = infinite)")
     progress_interval = Param.Tick('0',
         "print a progress message every n ticks (0 = never)")
diff --git a/src/python/m5/objects/System.py b/src/python/m5/objects/System.py
index 9a1e1d690..386f39277 100644
--- a/src/python/m5/objects/System.py
+++ b/src/python/m5/objects/System.py
@@ -1,9 +1,12 @@
 from m5 import build_env
 from m5.config import *
 
+class MemoryMode(Enum): vals = ['invalid', 'atomic', 'timing']
+
 class System(SimObject):
     type = 'System'
     physmem = Param.PhysicalMemory(Parent.any, "phsyical memory")
+    mem_mode = Param.MemoryMode('atomic', "The mode the memory system is in")
     if build_env['FULL_SYSTEM']:
         boot_cpu_frequency = Param.Frequency(Self.cpu[0].clock.frequency,
                                              "boot processor frequency")
diff --git a/src/python/m5/objects/Tsunami.py b/src/python/m5/objects/Tsunami.py
index 4613571d8..0b5ff9e7d 100644
--- a/src/python/m5/objects/Tsunami.py
+++ b/src/python/m5/objects/Tsunami.py
@@ -1,11 +1,10 @@
 from m5.config import *
 from Device import BasicPioDevice
 from Platform import Platform
-
-class Tsunami(Platform):
-    type = 'Tsunami'
-#    pciconfig = Param.PciConfigAll("PCI configuration")
-    system = Param.System(Parent.any, "system")
+from AlphaConsole import AlphaConsole
+from Uart import Uart8250
+from Pci import PciConfigAll
+from BadDevice import BadDevice
 
 class TsunamiCChip(BasicPioDevice):
     type = 'TsunamiCChip'
@@ -25,3 +24,71 @@ class TsunamiIO(BasicPioDevice):
 class TsunamiPChip(BasicPioDevice):
     type = 'TsunamiPChip'
     tsunami = Param.Tsunami(Parent.any, "Tsunami")
+
+class Tsunami(Platform):
+    type = 'Tsunami'
+    system = Param.System(Parent.any, "system")
+
+    cchip = TsunamiCChip(pio_addr=0x801a0000000)
+    pchip = TsunamiPChip(pio_addr=0x80180000000)
+    pciconfig = PciConfigAll()
+    fake_sm_chip = IsaFake(pio_addr=0x801fc000370)
+
+    fake_uart1 = IsaFake(pio_addr=0x801fc0002f8)
+    fake_uart2 = IsaFake(pio_addr=0x801fc0003e8)
+    fake_uart3 = IsaFake(pio_addr=0x801fc0002e8)
+    fake_uart4 = IsaFake(pio_addr=0x801fc0003f0)
+
+    fake_ppc = IsaFake(pio_addr=0x801fc0003bc)
+
+    fake_OROM = IsaFake(pio_addr=0x800000a0000, pio_size=0x60000)
+
+    fake_pnp_addr = IsaFake(pio_addr=0x801fc000279)
+    fake_pnp_write = IsaFake(pio_addr=0x801fc000a79)
+    fake_pnp_read0 = IsaFake(pio_addr=0x801fc000203)
+    fake_pnp_read1 = IsaFake(pio_addr=0x801fc000243)
+    fake_pnp_read2 = IsaFake(pio_addr=0x801fc000283)
+    fake_pnp_read3 = IsaFake(pio_addr=0x801fc0002c3)
+    fake_pnp_read4 = IsaFake(pio_addr=0x801fc000303)
+    fake_pnp_read5 = IsaFake(pio_addr=0x801fc000343)
+    fake_pnp_read6 = IsaFake(pio_addr=0x801fc000383)
+    fake_pnp_read7 = IsaFake(pio_addr=0x801fc0003c3)
+
+    fake_ata0 = IsaFake(pio_addr=0x801fc0001f0)
+    fake_ata1 = IsaFake(pio_addr=0x801fc000170)
+
+    fb = BadDevice(pio_addr=0x801fc0003d0, devicename='FrameBuffer')
+    io = TsunamiIO(pio_addr=0x801fc000000)
+    uart = Uart8250(pio_addr=0x801fc0003f8)
+    console = AlphaConsole(pio_addr=0x80200000000, disk=Parent.simple_disk)
+
+    # Attach I/O devices to specified bus object.  Can't do this
+    # earlier, since the bus object itself is typically defined at the
+    # System level.
+    def attachIO(self, bus):
+        self.cchip.pio = bus.port
+        self.pchip.pio = bus.port
+        self.pciconfig.pio = bus.default
+        self.fake_sm_chip.pio = bus.port
+        self.fake_uart1.pio = bus.port
+        self.fake_uart2.pio = bus.port
+        self.fake_uart3.pio = bus.port
+        self.fake_uart4.pio = bus.port
+        self.fake_ppc.pio = bus.port
+        self.fake_OROM.pio = bus.port
+        self.fake_pnp_addr.pio = bus.port
+        self.fake_pnp_write.pio = bus.port
+        self.fake_pnp_read0.pio = bus.port
+        self.fake_pnp_read1.pio = bus.port
+        self.fake_pnp_read2.pio = bus.port
+        self.fake_pnp_read3.pio = bus.port
+        self.fake_pnp_read4.pio = bus.port
+        self.fake_pnp_read5.pio = bus.port
+        self.fake_pnp_read6.pio = bus.port
+        self.fake_pnp_read7.pio = bus.port
+        self.fake_ata0.pio = bus.port
+        self.fake_ata1.pio = bus.port
+        self.fb.pio = bus.port
+        self.io.pio = bus.port
+        self.uart.pio = bus.port
+        self.console.pio = bus.port
author	Ali Saidi <saidi@eecs.umich.edu>	2006-07-19 17:59:04 -0400
committer	Ali Saidi <saidi@eecs.umich.edu>	2006-07-19 17:59:04 -0400
commit	15e5ce96c76a20b9b27e5f7d7ed29e962422ad1a (patch)
tree	610a888b2de5d25c166f65819d8ad3058d13723c /src/python
parent	b36796914af8bfc6729cc8a519e57572460e43e8 (diff)
parent	6175f712b3216f3e5387b07d9c41c1931c09acd9 (diff)
download	gem5-15e5ce96c76a20b9b27e5f7d7ed29e962422ad1a.tar.xz