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| author | Ron Dreslinski <rdreslin@umich.edu> | 2006-08-16 23:46:54 -0400 |
|---|---|---|
| committer | Ron Dreslinski <rdreslin@umich.edu> | 2006-08-16 23:46:54 -0400 |
| commit | 6eebfda2d9a4613d8357a2f266289311240a0a1b (patch) | |
| tree | 4bb45817a216962eed9506cd4fdb088b620a2902 /src/python | |
| parent | 3329f6f63910963bafd52244df16348667d2e6eb (diff) | |
| download | gem5-6eebfda2d9a4613d8357a2f266289311240a0a1b.tar.xz | |
Fix the caches not working in the regression
src/python/m5/objects/BaseCPU.py:
Make mem parameter a MemObject, not just a PhysicalMemory
Fix a reference not using self
tests/configs/simple-atomic.py:
Set the mem paramter
tests/configs/simple-timing.py:
Set the mem parameter
--HG--
extra : convert_revision : 6bd9df36831a1c5bafc9e88ab945c2ebe91db785
Diffstat (limited to 'src/python')
| -rw-r--r-- | src/python/m5/objects/BaseCPU.py | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/python/m5/objects/BaseCPU.py b/src/python/m5/objects/BaseCPU.py index 7906156a2..88a8bf5e3 100644 --- a/src/python/m5/objects/BaseCPU.py +++ b/src/python/m5/objects/BaseCPU.py @@ -6,7 +6,7 @@ from Bus import Bus class BaseCPU(SimObject): type = 'BaseCPU' abstract = True - mem = Param.PhysicalMemory(Parent.any, "memory") + mem = Param.MemObject(Parent.any, "memory") system = Param.System(Parent.any, "system object") if build_env['FULL_SYSTEM']: @@ -43,11 +43,12 @@ class BaseCPU(SimObject): self.icache_port = ic.cpu_side self.dcache_port = dc.cpu_side self._mem_ports = ['icache.mem_side', 'dcache.mem_side'] +# self.mem = dc def addTwoLevelCacheHierarchy(self, ic, dc, l2c): self.addPrivateSplitL1Caches(ic, dc) self.toL2Bus = Bus() self.connectMemPorts(self.toL2Bus) self.l2cache = l2c - self.l2cache.cpu_side = toL2Bus.port + self.l2cache.cpu_side = self.toL2Bus.port self._mem_ports = ['l2cache.mem_side'] |