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authorAli Saidi <saidi@eecs.umich.edu>2007-05-10 18:24:48 -0400
committerAli Saidi <saidi@eecs.umich.edu>2007-05-10 18:24:48 -0400
commit634d2e9d83054d2ddae4333d4e28e9a04cfbfd84 (patch)
treeb1d0e1a461306cf6f102bb1d039357326b0dbccd /src/python
parente08a5c60524d9e8d9a84d661c9464e3fe1289e2f (diff)
downloadgem5-634d2e9d83054d2ddae4333d4e28e9a04cfbfd84.tar.xz
remove hit_latency and make latency do the right thing
set the latency parameter in terms of a latency add caches to tsunami-simple configs configs/common/Caches.py: tests/configs/memtest.py: tests/configs/o3-timing-mp.py: tests/configs/o3-timing.py: tests/configs/simple-atomic-mp.py: tests/configs/simple-timing-mp.py: tests/configs/simple-timing.py: set the latency parameter in terms of a latency configs/common/FSConfig.py: give the bridge a default latency too src/mem/cache/cache_builder.cc: src/python/m5/objects/BaseCache.py: remove hit_latency and make latency do the right thing tests/configs/tsunami-simple-atomic-dual.py: tests/configs/tsunami-simple-atomic.py: tests/configs/tsunami-simple-timing-dual.py: tests/configs/tsunami-simple-timing.py: add caches to tsunami-simple configs --HG-- extra : convert_revision : 37bef7c652e97c8cdb91f471fba62978f89019f1
Diffstat (limited to 'src/python')
-rw-r--r--src/python/m5/objects/BaseCache.py3
1 files changed, 1 insertions, 2 deletions
diff --git a/src/python/m5/objects/BaseCache.py b/src/python/m5/objects/BaseCache.py
index 773a11bea..7df5215e4 100644
--- a/src/python/m5/objects/BaseCache.py
+++ b/src/python/m5/objects/BaseCache.py
@@ -9,7 +9,7 @@ class BaseCache(MemObject):
"Use an adaptive compression scheme")
assoc = Param.Int("associativity")
block_size = Param.Int("block size in bytes")
- latency = Param.Int("Latency")
+ latency = Param.Latency("Latency")
compressed_bus = Param.Bool(False,
"This cache connects to a compressed memory")
compression_latency = Param.Latency('0ns',
@@ -59,6 +59,5 @@ class BaseCache(MemObject):
"Use the CPU ID to seperate calculations of prefetches")
prefetch_data_accesses_only = Param.Bool(False,
"Only prefetch on data not on instruction accesses")
- hit_latency = Param.Int(1,"Hit Latency of the cache")
cpu_side = Port("Port on side closer to CPU")
mem_side = Port("Port on side closer to MEM")