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authorKevin Lim <ktlim@umich.edu>2006-07-05 16:08:18 -0400
committerKevin Lim <ktlim@umich.edu>2006-07-05 16:08:18 -0400
commitb973fae85d47a8184204d5d38b32ad3d427ce41c (patch)
treef101b7e4c91c1672bc21de12a4eb01e4120b1510 /src/python
parent4201ec84b2dd7d96148bf661124dd7b5d0e7204b (diff)
parentae78c465313d6ca1dc71e8b9731e952bb3c8c09b (diff)
downloadgem5-b973fae85d47a8184204d5d38b32ad3d427ce41c.tar.xz
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge src/base/traceflags.py: src/cpu/SConscript: Hand merge. src/cpu/o3/alpha/params.hh: Hand merge. This needs to get changed. --HG-- rename : src/cpu/o3/alpha_cpu_builder.cc => src/cpu/o3/alpha/cpu_builder.cc rename : src/cpu/o3/alpha_params.hh => src/cpu/o3/alpha/params.hh rename : src/python/m5/objects/AlphaO3CPU.py => src/python/m5/objects/O3CPU.py extra : convert_revision : 581f338f5bce35288f7d15d95cbd0ac3a9135e6a
Diffstat (limited to 'src/python')
-rw-r--r--src/python/m5/objects/O3CPU.py8
1 files changed, 3 insertions, 5 deletions
diff --git a/src/python/m5/objects/O3CPU.py b/src/python/m5/objects/O3CPU.py
index 4ecfa8fbd..9ccbdcf53 100644
--- a/src/python/m5/objects/O3CPU.py
+++ b/src/python/m5/objects/O3CPU.py
@@ -37,12 +37,10 @@ class DerivO3CPU(BaseCPU):
"Issue/Execute/Writeback delay")
issueToExecuteDelay = Param.Unsigned("Issue to execute delay (internal "
"to the IEW stage)")
+ dispatchWidth = Param.Unsigned("Dispatch width")
issueWidth = Param.Unsigned("Issue width")
- executeWidth = Param.Unsigned("Execute width")
- executeIntWidth = Param.Unsigned("Integer execute width")
- executeFloatWidth = Param.Unsigned("Floating point execute width")
- executeBranchWidth = Param.Unsigned("Branch execute width")
- executeMemoryWidth = Param.Unsigned("Memory execute width")
+ wbWidth = Param.Unsigned("Writeback width")
+ wbDepth = Param.Unsigned("Writeback depth")
fuPool = Param.FUPool(NULL, "Functional Unit pool")
iewToCommitDelay = Param.Unsigned("Issue/Execute/Writeback to commit "