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author | Ron Dreslinski <rdreslin@umich.edu> | 2006-06-30 17:21:58 -0400 |
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committer | Ron Dreslinski <rdreslin@umich.edu> | 2006-06-30 17:21:58 -0400 |
commit | 7a4929813423c6f72827c58453cb9bd591f1801c (patch) | |
tree | bddf49535c38df4e9faf12825861eee80c308229 /src/python | |
parent | 1bdc65b00f40b20dc5c7e97d3c8d8e4b311230a8 (diff) | |
download | gem5-7a4929813423c6f72827c58453cb9bd591f1801c.tar.xz |
AtomicSimpleCPU with a cache now runs the hello world! test program.
Need to clean up a bunch of flags/hacks in the code. Then onto Timming mode.
Functional accesses also work properly, although not exactly how we wanted them. I'll need to clean that up as well.
src/cpu/simple/atomic.cc:
Atomic CPU needs to set thread context so stats work in cache. Temporarily just use CPU=0 ThreadID=0
src/mem/cache/cache_impl.hh:
Need to return success/failure properly still
Physical memory object doesn't assert SATISFIED anymore, need to remove that flag
src/mem/cache/tags/lru.cc:
Doesn't work if the REQ doesn't set it's ASID. Temporary fix use 0 always
--HG--
extra : convert_revision : d06a39684af593db699b64df9a29f80c61d8d050
Diffstat (limited to 'src/python')
0 files changed, 0 insertions, 0 deletions