Merge with the main repo.

--HG--
rename : src/mem/vport.hh => src/mem/fs_translating_port_proxy.hh
rename : src/mem/translating_port.cc => src/mem/se_translating_port_proxy.cc
rename : src/mem/translating_port.hh => src/mem/se_translating_port_proxy.hh

2 files changed, 1 insertions, 6 deletions

diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py
index 47ca32af2..84d70d663 100644
--- a/src/python/m5/SimObject.py
+++ b/src/python/m5/SimObject.py
@@ -273,8 +273,6 @@ class MetaSimObject(type):
         assert(not hasattr(port, 'name'))
         port.name = name
         cls._ports[name] = port
-        if hasattr(port, 'default'):
-            cls._cls_get_port_ref(name).connect(port.default)
 
     # same as _get_port_ref, effectively, but for classes
     def _cls_get_port_ref(cls, attr):
diff --git a/src/python/m5/params.py b/src/python/m5/params.py
index 05fe9b774..dfc703a40 100644
--- a/src/python/m5/params.py
+++ b/src/python/m5/params.py
@@ -1488,13 +1488,10 @@ class VectorPortRef(object):
 # logical port in the SimObject class, not a particular port on a
 # SimObject instance.  The latter are represented by PortRef objects.
 class Port(object):
-    # Port("description") or Port(default, "description")
+    # Port("description")
     def __init__(self, *args):
         if len(args) == 1:
             self.desc = args[0]
-        elif len(args) == 2:
-            self.default = args[0]
-            self.desc = args[1]
         else:
             raise TypeError, 'wrong number of arguments'
         # self.name is set by SimObject class on assignment