diff options
| author | Steve Reinhardt <stever@eecs.umich.edu> | 2007-05-19 00:24:34 -0400 |
|---|---|---|
| committer | Steve Reinhardt <stever@eecs.umich.edu> | 2007-05-19 00:24:34 -0400 |
| commit | 0305159abf40765c6b8c506c777e3f62f3b6227e (patch) | |
| tree | 9e6f19f64d626708141076ebbb4daa44fbe513ba /src/python | |
| parent | a8278c3bde2ba9abc2820afafa9d0e766e36b2c8 (diff) | |
| download | gem5-0305159abf40765c6b8c506c777e3f62f3b6227e.tar.xz | |
PhysicalMemory has vector of uniform ports instead of one special one.
configs/example/memtest.py:
PhysicalMemory has vector of uniform ports instead of one special one.
Other updates to fix obsolete brokenness.
src/mem/physical.cc:
src/mem/physical.hh:
src/python/m5/objects/PhysicalMemory.py:
Have vector of uniform ports instead of one special one.
src/python/swig/pyobject.cc:
Add comment.
--HG--
extra : convert_revision : a4a764dcdcd9720bcd07c979d0ece311fc8cb4f1
Diffstat (limited to 'src/python')
| -rw-r--r-- | src/python/m5/objects/PhysicalMemory.py | 3 | ||||
| -rw-r--r-- | src/python/swig/pyobject.cc | 1 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/python/m5/objects/PhysicalMemory.py b/src/python/m5/objects/PhysicalMemory.py index c389e4a7f..83dbc7710 100644 --- a/src/python/m5/objects/PhysicalMemory.py +++ b/src/python/m5/objects/PhysicalMemory.py @@ -4,8 +4,7 @@ from MemObject import * class PhysicalMemory(MemObject): type = 'PhysicalMemory' - port = Port("the access port") - functional = Port("Functional Access Port") + port = VectorPort("the access port") range = Param.AddrRange(AddrRange('128MB'), "Device Address") file = Param.String('', "memory mapped file") latency = Param.Latency('1t', "latency of an access") diff --git a/src/python/swig/pyobject.cc b/src/python/swig/pyobject.cc index 11141fa84..2a5f2b9fb 100644 --- a/src/python/swig/pyobject.cc +++ b/src/python/swig/pyobject.cc @@ -62,6 +62,7 @@ lookupPort(SimObject *so, const std::string &name, int i) /** * Connect the described MemObject ports. Called from Python via SWIG. + * The indices i1 & i2 will be -1 for regular ports, >= 0 for vector ports. */ int connectPorts(SimObject *o1, const std::string &name1, int i1, |