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authorAli Saidi <saidi@eecs.umich.edu>2006-09-18 20:12:45 -0400
committerAli Saidi <saidi@eecs.umich.edu>2006-09-18 20:12:45 -0400
commit17b0e9714d4bde7462d4663899bb9498027f6b40 (patch)
tree464a837d850eb8e076e62d9a6926e9e57516b9d9 /src/python
parentb7d03951268d352254b918fbe1464954828ee8fd (diff)
downloadgem5-17b0e9714d4bde7462d4663899bb9498027f6b40.tar.xz
add boiler plate intel nic code
src/SConscript: add intel nic to sconscript src/dev/pcidev.cc: fix bug with subsystemid value src/python/m5/objects/Ethernet.py: add intel nic to ethernet.py src/python/m5/objects/Ide.py: src/python/m5/objects/Pci.py: Move config_latency into pci where it belogs --HG-- extra : convert_revision : 7163aaf7b4098496518b0910cef62f2ce3dd574d
Diffstat (limited to 'src/python')
-rw-r--r--src/python/m5/objects/Ethernet.py34
-rw-r--r--src/python/m5/objects/Ide.py2
-rw-r--r--src/python/m5/objects/Pci.py1
3 files changed, 33 insertions, 4 deletions
diff --git a/src/python/m5/objects/Ethernet.py b/src/python/m5/objects/Ethernet.py
index 609a3dd6f..f17a6c888 100644
--- a/src/python/m5/objects/Ethernet.py
+++ b/src/python/m5/objects/Ethernet.py
@@ -64,14 +64,44 @@ if build_env['ALPHA_TLASER']:
type = 'EtherDevInt'
device = Param.EtherDev("Ethernet device of this interface")
+
+class IGbE(PciDevice):
+ type = 'IGbE'
+ hardware_address = Param.EthernetAddr(NextEthernetAddr, "Ethernet Hardware Address")
+
+class IGbEPciData(PciConfigData):
+ VendorID = 0x8086
+ DeviceID = 0x1026
+ SubsystemID = 0x1008
+ SubsystemVendorID = 0x8086
+ Status = 0x0000
+ SubClassCode = 0x00
+ ClassCode = 0x02
+ ProgIF = 0x00
+ BAR0 = 0x00000000
+ BAR1 = 0x00000000
+ BAR2 = 0x00000000
+ BAR3 = 0x00000000
+ BAR4 = 0x00000000
+ BAR5 = 0x00000000
+ MaximumLatency = 0x00
+ MinimumGrant = 0xff
+ InterruptLine = 0x1e
+ InterruptPin = 0x01
+ BAR0Size = '128kB'
+
+class IGbEInt(EtherInt):
+ type = 'IGbEInt'
+ device = Param.IGbE("Ethernet device of this interface")
+
+
+
class EtherDevBase(PciDevice):
hardware_address = Param.EthernetAddr(NextEthernetAddr,
"Ethernet Hardware Address")
clock = Param.Clock('0ns', "State machine processor frequency")
- config_latency = Param.Latency('20ns', "Config read or write latency")
-
dma_read_delay = Param.Latency('0us', "fixed delay for dma reads")
dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
dma_write_delay = Param.Latency('0us', "fixed delay for dma writes")
diff --git a/src/python/m5/objects/Ide.py b/src/python/m5/objects/Ide.py
index 69681bdbd..ef7e28785 100644
--- a/src/python/m5/objects/Ide.py
+++ b/src/python/m5/objects/Ide.py
@@ -37,6 +37,4 @@ class IdeController(PciDevice):
type = 'IdeController'
disks = VectorParam.IdeDisk("IDE disks attached to this controller")
- config_latency = Param.Latency('20ns', "Config read or write latency")
-
configdata =IdeControllerPciData()
diff --git a/src/python/m5/objects/Pci.py b/src/python/m5/objects/Pci.py
index 9872532ab..55bf23534 100644
--- a/src/python/m5/objects/Pci.py
+++ b/src/python/m5/objects/Pci.py
@@ -56,6 +56,7 @@ class PciDevice(DmaDevice):
pci_func = Param.Int("PCI function code")
pio_latency = Param.Latency('1ns', "Programmed IO latency in simticks")
configdata = Param.PciConfigData(Parent.any, "PCI Config data")
+ config_latency = Param.Latency('20ns', "Config read or write latency")
class PciFake(PciDevice):
type = 'PciFake'