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| author | Ron Dreslinski <rdreslin@umich.edu> | 2006-08-21 13:20:35 -0400 |
|---|---|---|
| committer | Ron Dreslinski <rdreslin@umich.edu> | 2006-08-21 13:20:35 -0400 |
| commit | 689eb39d4862df05dacb5030494000230dcfb5a7 (patch) | |
| tree | e89869aba948c740a27629d12ea609b7235d7d1f /src/python | |
| parent | 21b21c63b02456276ebf3b49d61dc42156a20b8e (diff) | |
| parent | 825a7aadd24493e4cdf9590434134a31a8548cbe (diff) | |
| download | gem5-689eb39d4862df05dacb5030494000230dcfb5a7.tar.xz | |
Merge zizzer:/z/m5/Bitkeeper/newmem
into zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/newmem
src/python/m5/objects/BaseCPU.py:
Merge duplicate change
--HG--
extra : convert_revision : 214e57999ee78aadfc86e1f0b7198ff0d981ce16
Diffstat (limited to 'src/python')
| -rw-r--r-- | src/python/m5/objects/BaseCPU.py | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/python/m5/objects/BaseCPU.py b/src/python/m5/objects/BaseCPU.py index 81e09c94c..41e90b12b 100644 --- a/src/python/m5/objects/BaseCPU.py +++ b/src/python/m5/objects/BaseCPU.py @@ -43,6 +43,7 @@ class BaseCPU(SimObject): self.icache_port = ic.cpu_side self.dcache_port = dc.cpu_side self._mem_ports = ['icache.mem_side', 'dcache.mem_side'] +# self.mem = dc def addTwoLevelCacheHierarchy(self, ic, dc, l2c): self.addPrivateSplitL1Caches(ic, dc) |