summaryrefslogtreecommitdiff
path: root/src/python
diff options
context:
space:
mode:
authorGabe Black <gblack@eecs.umich.edu>2006-11-16 14:42:44 -0500
committerGabe Black <gblack@eecs.umich.edu>2006-11-16 14:42:44 -0500
commit74654ddd1f2233ab26c95d12f0fa73b7bb0f7c90 (patch)
tree44d9fc2d4fb84d45447df0d927111b2e6e3bacff /src/python
parentcd5b33b9ff4016427fa93655f4bbd9030c4f5612 (diff)
parent14ebaa1eccff4032d59147783e98e07b81b5f1ae (diff)
downloadgem5-74654ddd1f2233ab26c95d12f0fa73b7bb0f7c90.tar.xz
Merge zower.eecs.umich.edu:/home/gblack/m5/newmemmemops
into zower.eecs.umich.edu:/eecshome/m5/newmem --HG-- extra : convert_revision : 74b2352b8f088e38cd1ecf3a8233b45df0476d93
Diffstat (limited to 'src/python')
-rw-r--r--src/python/m5/objects/BaseCPU.py1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/python/m5/objects/BaseCPU.py b/src/python/m5/objects/BaseCPU.py
index 2f702a4bf..8037c90af 100644
--- a/src/python/m5/objects/BaseCPU.py
+++ b/src/python/m5/objects/BaseCPU.py
@@ -47,6 +47,7 @@ class BaseCPU(SimObject):
"defer registration with system (for sampling)")
clock = Param.Clock(Parent.clock, "clock speed")
+ phase = Param.Latency("0ns", "clock phase")
_mem_ports = []